Analytical Drain Current Model for Amorphous and Polycrystalline Silicon Thin-Film Transistors at Different Temperatures Considering Both Deep and Tail Trap States

Author(s):  
Hongyu He ◽  
Yuan Liu ◽  
Binghui Yan ◽  
Xinnan Lin ◽  
Xueren Zheng ◽  
...  
2008 ◽  
Vol 47 (10) ◽  
pp. 7798-7802 ◽  
Author(s):  
Hiroshi Tsuji ◽  
Tsuyoshi Kuzuoka ◽  
Yuji Kishida ◽  
Yoshiyuki Shimizu ◽  
Masaharu Kirihara ◽  
...  

2008 ◽  
Vol 22 (30) ◽  
pp. 5357-5364
Author(s):  
NAVNEET GUPTA

This work presents the study of the effect of trap states at the oxide-silicon interface in lightly doped polycrystalline silicon thin-film transistors with large grains. In this study, it is assumed that the oxide-silicon interface traps are evenly distributed throughout the interface region and single grain boundary is present in the channel of poly-Si TFT. It is shown that improved device characteristics can be obtained by reducing the gate oxide thickness. It is also observed that as gate oxide thickness decreases for a constant value of trap state density in the oxide-silicon interface, the gate voltage required for channel formation is lowered and leads to a decrease in threshold voltage of the device. Calculated and experimental results are also found to be well consistent with each other.


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