Decreasing test time by scan chain reorganization

2011 ◽  
Author(s):  
Pavel Bartos ◽  
Zdenek Kotasek ◽  
Jan Dohnal
Keyword(s):  
Test Time ◽  
Scan Chain

Improving Yield Using Scan and DFT Based Analysis for High Performance PowerPC© Microprocessor

2006 ◽  
Author(s):  
Ray Talacka ◽  
Nandu Tendolkar ◽  
Cynthia Paquette
Keyword(s):  
High Performance ◽  
Yield Enhancement ◽  
Test Time ◽  
Balance Test ◽  
Specific Test ◽  
Defect Location ◽  
Test Methodology ◽  
Memory Arrays ◽  
Scan Chain ◽  
Scan Pattern

Abstract The use of memory arrays to drive yield enhancement has driven the development of many technologies. The uniformity of the arrays allows for easy testing and defect location. Unfortunately, the complexities of the logic circuitry are not represented well in the memory arrays. As technologies push to smaller geometries and the layout and timing of the logic circuitry become more problematic the ability to address yield issue is becoming critical. This paper presents the added yield enhancement capabilities of using e600 core Scan Chain and Scan Pattern testing for logic debug, ways to interpret the fail data, and test methodologies to balance test time and acquiring data. Selecting a specific test methodology and using today's advanced tools like Freescale's DFT/FA has been proven to find more yield issues, earlier, enabling quicker issue resolution.

A New Wrapper Scan Chain Balance Algorithm for Intellectual Property in SoC

2014 ◽  
Vol 8 (1) ◽  
pp. 42-49
Author(s):  
Aijun Zhu ◽  
Zhi Li ◽  
Chuanpei Xu ◽  
Wangchun Zhu
Keyword(s):  
Intellectual Property ◽  
Optimization Algorithm ◽  
Test Time ◽  
Test Cost ◽  
Opposition Based Learning ◽  
Random Optimization ◽  
Mutation Operation ◽  
Scan Chains ◽  
Scan Chain ◽  
On Chip

Recent patents and progress on scan chain balance algorithms have been reviewed. With a significant increase of the SoC (System on Chip) integration and scale, the test time of SoC increase dramatically, and this makes the test cost of SoC grow rapidly. In order to reduce test cost and expense, the paper proposes an OBBO (Opposition-based learning and Biogeography Based Optimization) algorithm and designs wrapper scan chains for the IP(Intellectual Property) using OBBO algorithm, which can make wrapper scan chains equilibration so that we can make the test time of IP be minimum. The new method is a random optimization algorithm which combines BBO (Biogeography Based Optimization) algorithm with OBL (Opposition-based learning). By using migration operation, mutation operation and OBL operation, we achieve a balance between different wrapper chains so that we can shorten the wrapper scan chain which is longest. Experimental results show that OBBO can obtain shorter longest wrapper scan chain in most case and at the same time the convergence speed can be faster.

On a Method of Getting Test Data for Boundary Scan Interconnection Test in Multiple Scan Chains

2014 ◽  
Vol 986-987 ◽  
pp. 1531-1535
Author(s):  
Xian Hua Yin ◽  
Cui Feng Xu
Keyword(s):  
Test Data ◽  
Test Time ◽  
Sorting Algorithm ◽  
Boundary Scan ◽  
Circuit Boards ◽  
Project Description ◽  
Description File ◽  
Multiple Scan ◽  
Scan Chains ◽  
Scan Chain

The goal of this paper is to present a new innovative method of getting test data for boundary scan interconnection test in multiple scan chains, so to decrease the test time and increase the efficiency and reliability. Firstly, a new model of configuring and optimizing multiple scan chains is formed based on the researches on greedy strategy for configuring multiple scan chains for internal test and the sorting algorithm of single scan chain for Cluster test. Then, a method of establishing test project description file (TPDF) is presented in order to get the test data quickly and effectively. During the testing of two different boundary-scan circuit boards, all faults can be detected. Experiment results show that the expected objective is achieved.

Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks

2021 ◽  
Vol 26 (4) ◽  
pp. 1-27
Author(s):  
M Sazadur Rahman ◽  
Adib Nahiyan ◽  
Fahim Rahman ◽  
Saverio Fazzari ◽  
Kenneth Plaks ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Formal Proof ◽  
Test Time ◽  
Security Assessment ◽  
Combinational Circuit ◽  
Promising Solution ◽  
Logic Locking ◽  
Scan Chain ◽  
Key Extraction ◽  
Time Overhead

Logic locking has emerged as a promising solution to protect integrated circuits against piracy and tampering. However, the security provided by existing logic locking techniques is often thwarted by Boolean satisfiability (SAT)-based oracle-guided attacks. Criteria for successful SAT attacks on locked circuits include: (i) the circuit under attack is fully combinational, or (ii) the attacker has scan chain access. To address the threat posed by SAT-based attacks, we adopt the dynamically obfuscated scan chain (DOSC) architecture and illustrate its resiliency against the SAT attacks when inserted into the scan chain of an obfuscated design. We demonstrate, both mathematically and experimentally, that DOSC exponentially increases the resiliency against key extraction by SAT attack and its variants. Our results show that the mathematical estimation of attack complexity correlates to the experimental results with an accuracy of 95% or better. Along with the formal proof, we model DOSC architecture to its equivalent combinational circuit and perform SAT attack to evaluate its resiliency empirically. Our experiments demonstrate that SAT attack on DOSC-inserted benchmark circuits timeout at minimal test time overhead, and while DOSC requires less than 1% area and power overhead.

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