Performance modeling and optimization for on-chip interconnects in cross-bar ReRAM memory arrays

Author(s):  
Javaneh Mohseni ◽  
Chenyun Pan ◽  
Azad Naeemi
2006 ◽  
Author(s):  
Xin Li ◽  
Jiayong Le ◽  
Lawrence T Pileggi

2018 ◽  
Vol 34 ◽  
pp. 104-115 ◽  
Author(s):  
A. Eliseus ◽  
Z.A. Putra ◽  
M.R. Bilad ◽  
N.A.H.M. Nordin ◽  
M.D.H. Wirzal ◽  
...  

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