A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories

2010 Proceedings of ESSCIRC ◽

10.1109/esscirc.2010.5619799 ◽

2010 ◽

Author(s):

T. Tanzawa ◽

T. Tanaka ◽

S. Tamada ◽

J. Kishimoto ◽

S. Yamada ◽

...

Keyword(s):

Temperature Compensation ◽

Flash Memories ◽

Line Voltage ◽

Voltage Generator ◽

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Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories

2006 IEEE Workshop on Signal Processing Systems Design and Implementation ◽

10.1109/sips.2006.352599 ◽

2006 ◽

Author(s):

Wei Liu ◽

Junrye Rho ◽

Wonyong Sung

Keyword(s):

Low Power ◽

Error Correction ◽

High Throughput ◽

Vlsi Design ◽

Flash Memories ◽

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A double-level-V/sub th/ select gate array architecture for multi-level NAND flash memories

Digest of Technical Papers., Symposium on VLSI Circuits. ◽

10.1109/vlsic.1995.520689 ◽

2002 ◽

Author(s):

K. Takeuchi ◽

T. Tanaka ◽

H. Nakamura

Keyword(s):

Flash Memories ◽

Array Architecture ◽

Multi Level ◽

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Program word-line voltage generator for multilevel flash memories

ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445) ◽

10.1109/icecs.2000.913051 ◽

2002 ◽

Author(s):

O. Khouri ◽

R. Micheloni ◽

A. Sacco ◽

G. Campardo ◽

G. Torelli

Keyword(s):

Flash Memories ◽

Line Voltage ◽

Voltage Generator

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A Multi-page Cell Architecture For High-speed Programming Multi-level NAND Flash Memories

Symposium on VLSI Circuits ◽

10.1109/vlsic.1997.623810 ◽

1997 ◽

Author(s):

Takeuchi ◽

Tanaka ◽

Tanzawa

Keyword(s):

Flash Memories ◽

Cell Architecture ◽

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Comparison of TID response and SEE characterization of single- and multi-level high density NAND flash memories

2009 European Conference on Radiation and Its Effects on Components and Systems ◽

10.1109/radecs.2009.5994731 ◽

2009 ◽

Author(s):

Farokh Irom ◽

Duc N. Nguyen ◽

Reno Harboe-Sorensen ◽

Ari Virtanen

Keyword(s):

High Density ◽

Flash Memories ◽

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A Small Ripple and High-Efficiency Wordline Voltage Generator for 3-D NAND Flash Memories

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2021.3113980 ◽

2021 ◽

pp. 1-9

Author(s):

Qianqian Wang ◽

Fei Liu ◽

Cece Huang ◽

Qianhui Li ◽

Zongliang Huo

Keyword(s):

High Efficiency ◽

Flash Memories ◽

Voltage Generator

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A Negative Word-line Voltage Step-Down Erase Pulse Scheme with ΔVTH=⅙ ΔVERASE for Enterprise SSD Application Ferroelectric(Fe)-NAND Flash Memories

10.7567/ssdm.2009.g-6-2 ◽

2009 ◽

Author(s):

R. Yajima ◽

T. Hatanaka ◽

M. Takahashi ◽

S. Sakai ◽

K. Takeuchi

Keyword(s):

Negative Word ◽

Flash Memories ◽

Voltage Step ◽

Line Voltage ◽

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A Negative Word-Line Voltage Negatively-Incremental Erase Pulse Scheme with ΔVTH= 1/6ΔVERASEfor Enterprise Solid-State Drive Application Ferroelectric-NAND Flash Memories

Japanese Journal of Applied Physics ◽

10.1143/jjap.49.04dd08 ◽

2010 ◽

Vol 49 (4) ◽

pp. 04DD08 ◽

Author(s):

Teruyoshi Hatanaka ◽

Ryoji Yajima ◽

Mitsue Takahashi ◽

Shigeki Sakai ◽

Ken Takeuchi

Keyword(s):

Solid State ◽

Negative Word ◽

Solid State Drive ◽

Flash Memories ◽

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Performance Enhancement of Polar Codes in Multi-level Cell NAND Flash Memories using Systematic Encoding

2019 19th International Symposium on Communications and Information Technologies (ISCIT) ◽

10.1109/iscit.2019.8905168 ◽

2019 ◽

Author(s):

Duc-Phuc Nguyen ◽

Khoa Le ◽

Fakhreddine Ghaffari ◽

David Declercq

Keyword(s):

Performance Enhancement ◽

Polar Codes ◽

Flash Memories ◽

Multi Level ◽

Systematic Encoding

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Evaluation of Mechanisms in TID Degradation and SEE Susceptibility of Single- and Multi-Level High Density NAND Flash Memories

IEEE Transactions on Nuclear Science ◽

10.1109/tns.2011.2161885 ◽

2011 ◽

Vol 58 (5) ◽

pp. 2477-2482 ◽

Author(s):

Farokh Irom ◽

Duc N. Nguyen ◽

Reno Harboe-Sorensen ◽

Ari Virtanen

Keyword(s):

High Density ◽

Flash Memories ◽

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