Impact of printed circuit board technology on thermal performance of high-power LED assembly - experimental results

Author(s):  
Johann Nicolics ◽  
Gregor Langer ◽  
Ferdinand Lutschounig ◽  
Kurt-Jurgen Lang ◽  
Rainer Huber
2019 ◽  
Vol 141 (5) ◽  
Author(s):  
Sangbeom Cho ◽  
Yogendra Joshi

We develop a vapor chamber integrated with a microelectronic packaging substrate and characterize its heat transfer performance. A prototype of vapor chamber integrated printed circuit board (PCB) is fabricated through successful completion of the following tasks: patterning copper micropillar wick structures on PCB, mechanical design and fabrication of condenser, device sealing, and device vacuuming and charging with working fluid. Two prototype vapor chambers with distinct micropillar array designs are fabricated, and their thermal performance tested under various heat inputs supplied from a 2 mm × 2 mm heat source. Thermal performance of the device improves with heat inputs, with the maximum performance of ∼20% over copper plated PCB with the same thickness. A three-dimensional computational fluid dynamics/heat transfer (CFD/HT) numerical model of the vapor chamber, coupled with the conduction model of the packaging substrate is developed, and the results are compared with test data.


Nano Research ◽  
2014 ◽  
Vol 8 (3) ◽  
pp. 722-730 ◽  
Author(s):  
Changbao Han ◽  
Chi Zhang ◽  
Wei Tang ◽  
Xiaohui Li ◽  
Zhong Lin Wang

2019 ◽  
Vol 141 (4) ◽  
Author(s):  
John H. Lau

The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.


Author(s):  
John F. Maddox ◽  
Roy W. Knight ◽  
Sushil H. Bhavnani

The thermal performance of an electronic device is heavily dependent on the properties of the printed circuit board (PCB) to which it is attached. However, even small variations in the process used to fabricate a PCB can have drastic effects on its thermal properties. Therefore, it is necessary to experimentally verify that each stage in the manufacturing process is producing the desired result. Steady state thermal resistance measurements, taken with a comparative cut bar apparatus based on ASTM D 5470-06, were used to compare PCBs manufactured from the same design by different vendors and the effects of vias filled with epoxy versus unfilled vias on the thermal resistance of a PCB. It was found that the thermal resistance of the PCBs varied by as much as 30% between vendors and that the PCBs with epoxy filled vias had a higher thermal resistance than those with unfilled vias, possibly due to the order in which the manufacturing steps were taken.


Author(s):  
Tomoyuki Hatakeyama ◽  
Masaru Ishizuka ◽  
Shinji Nakagawa ◽  
Sadakazu Takakuwa

Thermal vias are widely used to reduce thermal resistance of a printed circuit board (PCB). However, fine via structure becomes an obstacle to computational fluid dynamics (CFD) simulation because fine structure requires a huge number of meshes. Therefore, an efficient modeling method of thermal via structure is needed to reduce computational time. In this paper, an effect of thermal vias on reduction of thermal resistance was experimentally and numerically investigated to gather fundamental data for thermal management of electronics. We used printed circuit board models with some kind of arrangements of thermal vias. Board materials and copper dissipating pad patterns were explored as experimental parameters. Copper pipes (unfilled vias) or rods (filled vias), the diameter of which was 1.5, 3.0 and 5.0 mm, were used as thermal via. Three materials (Glass epoxy, Stainless, and Polycarbonate), thermal conductivity of which were different, were used as board materials. The experimental results showed that area of heat dissipating copper pad patterns and board materials have strong effect on the temperature rise of the heat source. On the other hand, the number of thermal vias and via shapes have no effect on the heat source temperature. Then we performed thermal network analysis to evaluate the experimental results. From the results of the thermal network analysis, it was confirmed that an effect of thermal via is saturated at certain ratio of via area.


2001 ◽  
Author(s):  
V. H. Adams ◽  
T.-Y. Tom Lee

Abstract Alternative interconnect strategies are being considered in place of the standard wire bond interconnect for GaAs power amplifier MMIC devices due to cost and electrical performance improvements. The package/die thermal performance consequences are potentially high-risk issue to these interconnect strategies and requires evaluation. Thermal simulations are conducted to compare and evaluate the thermal performances of three interconnect strategies: wire bond, gold post-flip chip, and through via interconnects. The test vehicle simulated is a three-stage, dual band power amplifier integrated circuit dissipating approximately 5 W steady-state power. Parametric studies are conducted to evaluate the impact of the printed circuit board, die thickness, solid gold vias, and design enhancements on package thermal performance. Best thermal performance is provided by a wire bonded, thin GaAs die attached with solder die attach to a printed circuit board that maximizes the number of plated-through-holes directly under the die. This configuration results in a best case junction-to-heat sink thermal resistance of 12 °C/W. Optimum flip chip and through via designs result in degraded thermal performance compared to the above described wire bond design but may have acceptable thermal performance. For these simulations, predicted junction-to-heatsink thermal resistance is in a range of 15–20 °C/W and is better than a comparable wire bonded design that uses a conductive epoxy die attach material.


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