McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs

The class of buildings designated as commercial is comprised of many different architectures and functions, which presents a challenge when developing demand management strategies that are applicable across this field. Most advanced controllers are based on a model of the thermal loads in the building envelope. These models do not directly extrapolate to measures of power consumption, which is what building owners are ultimately interested in managing. In this work, we develop models of power use that can be easily tailored to model power demand in any commercial building with advanced sensing and metering. We address how existing models of the building temperature states can be incorporated into our framework. Specifically, we show how Auto-Regressive models with eXogeneous (ARX) inputs can be used for superior day-ahead forecasting of demand, and how to formulate the models in a way that is meaningful at the supervisory level. These models provide more flexibility in the design of a supervisory controller for building energy management and the information they provide is crucial for bridging the gap between buildings and utilities in the smart grid.

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McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2014.2352354 ◽

2015 ◽

Vol 23 (9) ◽

pp. 1616-1627 ◽

Cited By ~ 12

Author(s):

Aoxiang Tang ◽

Yang Yang ◽

Chun-Yi Lee ◽

Niraj K. Jha

Keyword(s):

Power Modeling ◽

Modeling Framework ◽

Processor Architectures ◽

Pvt Variations

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Power Modeling Framework for an Asynchronous Processor

Journal of Circuits System and Computers ◽

10.1142/s0218126616500572 ◽

2016 ◽

Vol 25 (06) ◽

pp. 1650057

Author(s):

Je-Hoon Lee

Keyword(s):

Power Consumption ◽

High Accuracy ◽

The Other ◽

Power Model ◽

Power Modeling ◽

Modeling Framework ◽

Low Level ◽

Architectural Model ◽

Power Models

This paper presents two power models for an asynchronous processor, A8051. The first one is a pipeline accurate model which models power consumption at each pipeline stage. The other one is a micro-architectural model which models power consumption at micro-operation level. Then, we demonstrate the feasibility of the proposed approach on an A8051 processor case study. The experimental results based on applying the proposed pipeline-accurate and micro-architectural power models on an A8051 processor demonstrate that the proposed power models have high accuracy with simulation times much faster than the conventional low-level power simulator. It also shows similar results compared to the conventional power model for a synchronous processor. Even though the simulation speeds for the proposed power models are approximately 100–900 times faster than the low-level power simulator, the differences are less than 18% and 15%, respectively. Thus, the proposed power models can give a guide for SoC designers who want to integrate the asynchronous processor for low-power SoC design.

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