Profiling-Based Control-Flow Reduction in High-Level Synthesis

2021 ◽  
Author(s):  
Austin Liolli ◽  
Omar Ragheb ◽  
Jason Anderson
Keyword(s):  
Control Flow ◽  
High Level Synthesis ◽  
Flow Reduction ◽  
High Level

scholarly journals Buffer Placement and Sizing for High-Performance Dataflow Circuits

2022 ◽  
Vol 15 (1) ◽  
pp. 1-32
Author(s):  
Lana Josipović ◽  
Shabnam Sheikhha ◽  
Andrea Guerrieri ◽  
Paolo Ienne ◽  
Jordi Cortadella
Keyword(s):  
Performance Optimization ◽  
Optimization Model ◽  
High Performance ◽  
Control Flow ◽  
High Level Synthesis ◽  
Software Applications ◽  
Marked Graphs ◽  
Variable Latency ◽  
High Level ◽  
Strong Contrast

Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches), unpredictable memory dependencies, and irregular control flow. Dataflow circuits exhibit an unconventional property: registers (usually referred to as “buffers”) can be placed anywhere in the circuit without changing its semantics, in strong contrast to what happens in traditional datapaths. Yet, although functionally irrelevant, this placement has a significant impact on the circuit’s timing and throughput. In this work, we show how to strategically place buffers into a dataflow circuit to optimize its performance. Our approach extracts a set of choice-free critical loops from arbitrary dataflow circuits and relies on the theory of marked graphs to optimize the buffer placement and sizing. Our performance optimization model supports important high-level synthesis features such as pipelined computational units, units with variable latency and throughput, and if-conversion. We demonstrate the performance benefits of our approach on a set of dataflow circuits obtained from imperative code.

High-level synthesis of low-power control-flow intensive circuits

1999 ◽  
Vol 18 (12) ◽  
pp. 1715-1729 ◽  
Author(s):  
K.S. Khouri ◽  
G. Lakshminarayana ◽  
N.K. Jha
Keyword(s):  
Low Power ◽  
Power Control ◽  
Control Flow ◽  
High Level Synthesis ◽  
High Level

Combined control flow dominated and data flow dominated high-level synthesis

2005 ◽  
Author(s):  
E. Berrebi ◽  
P. Kission ◽  
S. Vernalde ◽  
S. De Troch ◽  
J.C. Berluison ◽  
...  
Keyword(s):  
Data Flow ◽  
Control Flow ◽  
High Level Synthesis ◽  
Combined Control ◽  
High Level

Combined control flow dominated and data flow dominated high-level synthesis

1996 ◽  
Author(s):  
E. Berrebi ◽  
P. Kission ◽  
S. Vernalde ◽  
S. De Troch ◽  
J. C. Herluison ◽  
...  
Keyword(s):  
Data Flow ◽  
Control Flow ◽  
High Level Synthesis ◽  
Combined Control ◽  
High Level

scholarly journals Formal verification of high-level synthesis

2021 ◽  
Vol 5 (OOPSLA) ◽  
pp. 1-30
Author(s):  
Yann Herklotz ◽  
James D. Pollard ◽  
Nadesh Ramanathan ◽  
John Wickerson
Keyword(s):  
Control Flow ◽  
High Level Synthesis ◽  
Function Calls ◽  
Comparable Performance ◽  
Order Of Magnitude ◽  
Hardware Description ◽  
The Rich ◽  
High Level ◽  
Hardware Designs ◽  
Application Specific

High-level synthesis (HLS), which refers to the automatic compilation of software into hardware, is rapidly gaining popularity. In a world increasingly reliant on application-specific hardware accelerators, HLS promises hardware designs of comparable performance and energy efficiency to those coded by hand in a hardware description language such as Verilog, while maintaining the convenience and the rich ecosystem of software development. However, current HLS tools cannot always guarantee that the hardware designs they produce are equivalent to the software they were given, thus undermining any reasoning conducted at the software level. Furthermore, there is mounting evidence that existing HLS tools are quite unreliable, sometimes generating wrong hardware or crashing when given valid inputs. To address this problem, we present the first HLS tool that is mechanically verified to preserve the behaviour of its input software. Our tool, called Vericert, extends the CompCert verified C compiler with a new hardware-oriented intermediate language and a Verilog back end, and has been proven correct in Coq. Vericert supports most C constructs, including all integer operations, function calls, local arrays, structs, unions, and general control-flow statements. An evaluation on the PolyBench/C benchmark suite indicates that Vericert generates hardware that is around an order of magnitude slower (only around 2× slower in the absence of division) and about the same size as hardware generated by an existing, optimising (but unverified) HLS tool.

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

2009 ◽  
Vol E92-A (12) ◽  
pp. 3169-3179 ◽  
Author(s):  
Akira OHCHI ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI
Keyword(s):  
High Level Synthesis ◽  
High Level
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