Proceedings Design, Automation and Test in Europe
Latest Publications

TOTAL DOCUMENTS

171

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Published By IEEE Comput. Soc

0818683597

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Silicon Debug of Systems-on-Chips

Proceedings Design, Automation and Test in Europe ◽

10.1109/date.1998.655924 ◽

2005 ◽

Cited By ~ 1

Author(s):

K. van Doorselaer ◽

S. Narayanan ◽

G.J. van Rootselaar ◽

E.J. Marinissen

Keyword(s):

Silicon Debug

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Innovative system-level design environment based on FORM for transport processing system

Proceedings Design, Automation and Test in Europe ◽

10.1109/date.1998.655962 ◽

2002 ◽

Cited By ~ 4

Author(s):

K. Higuchi ◽

K. Shirakawa

Keyword(s):

Processing System ◽

System Level ◽

System Level Design ◽

Design Environment ◽

Innovative System ◽

Level Design

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A systematic analysis of reuse strategies for design of electronic circuits

Proceedings Design, Automation and Test in Europe ◽

10.1109/date.1998.655871 ◽

2002 ◽

Cited By ~ 14

Author(s):

M. Koegst ◽

P. Conradi ◽

D. Garte ◽

M. Wahl

Keyword(s):

Electronic Circuits ◽

Systematic Analysis

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A dynamic model for the state assignment problem

Proceedings Design, Automation and Test in Europe ◽

10.1109/date.1998.655955 ◽

2002 ◽

Cited By ~ 5

Author(s):

M. Martinez ◽

M.J. Avedillo ◽

J.M. Quintana ◽

J.L. Huertas

Keyword(s):

Dynamic Model ◽

Assignment Problem ◽

The State ◽

State Assignment

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Correct high-level synthesis: a formal perspective

Proceedings Design, Automation and Test in Europe ◽

10.1109/date.1998.655997 ◽

2002 ◽

Cited By ~ 4

Author(s):

J.M. Mendias ◽

R. Hermida ◽

M. Fernandez

Keyword(s):

High Level Synthesis ◽

High Level

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An effective general connectivity concept for clustering

Proceedings Design, Automation and Test in Europe ◽

10.1109/date.1998.655888 ◽

2002 ◽

Author(s):

Jianjian Song ◽

Zhaoxuan Shen ◽

Wenjun Zhuang

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Collapsing the transistor chain to an effective single equivalent transistor

Proceedings Design, Automation and Test in Europe ◽

10.1109/date.1998.655829 ◽

2002 ◽

Cited By ~ 9

Author(s):

A. Chatzigeorgiou ◽

S. Nikolaidis

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Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking

Proceedings Design, Automation and Test in Europe ◽

10.1109/date.1998.655928 ◽

2002 ◽

Cited By ~ 9

Author(s):

D. Ghosh ◽

N. Kapur ◽

J. Harlow ◽

F. Brglez

Keyword(s):

Equivalence Class

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Core interconnect testing hazards

Proceedings Design, Automation and Test in Europe ◽

10.1109/date.1998.655985 ◽

2002 ◽

Author(s):

P. Nordholz ◽

H. Grabinski ◽

D. Treytnar ◽

J. Otterstedt ◽

D. Niggemeyer ◽

...

Keyword(s):

Interconnect Testing

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Design methodologies for system level IP

Proceedings Design, Automation and Test in Europe ◽

10.1109/date.1998.655869 ◽

2002 ◽

Cited By ~ 27

Author(s):

G. Martin

Keyword(s):

System Level ◽

Design Methodologies

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Proceedings Design, Automation and Test in EuropeLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Silicon Debug of Systems-on-Chips

Innovative system-level design environment based on FORM for transport processing system

A systematic analysis of reuse strategies for design of electronic circuits

A dynamic model for the state assignment problem

Correct high-level synthesis: a formal perspective

An effective general connectivity concept for clustering

Collapsing the transistor chain to an effective single equivalent transistor

Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking

Core interconnect testing hazards

Design methodologies for system level IP

Proceedings Design, Automation and Test in Europe
Latest Publications