Efficient IR drop analysis and alleviation methodologies using dual threshold voltages with gate resizing techniques

Author(s):  
Yap-Chung Phong ◽  
Ching-Hwa Cheng ◽  
Jiun-In Guo
2015 ◽  
Vol 10 (3) ◽  
pp. 147-157
Author(s):  
Ching-Hwa Cheng

IR drop impacts circuit delay time and reliability. The IR drop comes from unexpected peak current (Ipeak) consumption. This paper proposes an efficient methodology with an in-house EDA tool named IPR to analyze and reduce the Ipeak. IPR adopts dual threshold voltages (Vth) and gate resizing technique; it also lowers the short, dynamic, and static leakage current consumption without degrading the system performance. IPR consists of two parts: Ipeak analysis and Ipeak alleviation processes. Nonlinear static/dynamic timing analysis techniques, in cooperation with dual Vth cell library, provides two kinds of accurate Ipeak calculation methods used in IPR. Using the incremental timing analysis, the Ipeak processing time can be accelerated. Demonstration of the ISCAS89 benchmark circuits shows that IPR can reduce Ipeak by 39%, power consumption by 14%, and delay time by 19%. In addition, it provides 334 times faster computation with 2% and 10% estimation errors of the Ipeak and power in gate-level, respectively, as compared to circuit level simulation results.


Author(s):  
Yih-Cheng Shih ◽  
E. L. Wilkie

Tungsten silicides (WSix) have been successfully used as the gate materials in self-aligned GaAs metal-semiconductor-field- effect transistors (MESFET). Thermal stability of the WSix/GaAs Schottky contact is of major concern since the n+ implanted source/drain regions must be annealed at high temperatures (∼ 800°C). WSi0.6 was considered the best composition to achieve good device performance due to its low stress and excellent thermal stability of the WSix/GaAs interface. The film adhesion and the uniformity in barrier heights and ideality factors of the WSi0.6 films have been improved by depositing a thin layer of pure W as the first layer on GaAs prior to WSi0.6 deposition. Recently WSi0.1 has been used successfully as the gate material in 1x10 μm GaAs FET's on the GaAs substrates which were sputter-cleaned prior to deposition. These GaAs FET's exhibited uniform threshold voltages across a 51 mm wafer with good film adhesion after annealing at 800°C for 10 min.


2021 ◽  
pp. 1-1
Author(s):  
Junting Chen ◽  
Mengyuan Hua ◽  
Chengcai Wang ◽  
Ling Liu ◽  
Lingling Li ◽  
...  

Coatings ◽  
2021 ◽  
Vol 11 (3) ◽  
pp. 318
Author(s):  
Yang Li ◽  
Cheng Zhang ◽  
Zhiming Shi ◽  
Jingni Li ◽  
Qingyun Qian ◽  
...  

The explosive growth of data and information has increasingly motivated scientific and technological endeavors toward ultra-high-density data storage (UHDDS) applications. Herein, a donor−acceptor (D–A) type small conjugated molecule containing benzothiadiazole (BT) is prepared (NIBTCN), which demonstrates multilevel resistive memory behavior and holds considerable promise for implementing the target of UHDDS. The as-prepared device presents distinct current ratios of 105.2/103.2/1, low threshold voltages of −1.90 V and −3.85 V, and satisfactory reproducibility beyond 60%, which suggests reliable device performance. This work represents a favorable step toward further development of highly-efficient D−A molecular systems, which opens more opportunities for achieving high performance multilevel memory materials and devices.


2019 ◽  
Vol 50 (S1) ◽  
pp. 985-987
Author(s):  
Junting Ouyang ◽  
Bojia Lyu ◽  
DZ Peng ◽  
Kang Yang ◽  
Xiangzi Kong ◽  
...  
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