Efficient IR Drop Analysis and Alleviation Methodologies Using Dual Threshold Voltages with Gate Resizing Techniques

IR drop impacts circuit delay time and reliability. The IR drop comes from unexpected peak current (Ipeak) consumption. This paper proposes an efficient methodology with an in-house EDA tool named IPR to analyze and reduce the Ipeak. IPR adopts dual threshold voltages (Vth) and gate resizing technique; it also lowers the short, dynamic, and static leakage current consumption without degrading the system performance. IPR consists of two parts: Ipeak analysis and Ipeak alleviation processes. Nonlinear static/dynamic timing analysis techniques, in cooperation with dual Vth cell library, provides two kinds of accurate Ipeak calculation methods used in IPR. Using the incremental timing analysis, the Ipeak processing time can be accelerated. Demonstration of the ISCAS89 benchmark circuits shows that IPR can reduce Ipeak by 39%, power consumption by 14%, and delay time by 19%. In addition, it provides 334 times faster computation with 2% and 10% estimation errors of the Ipeak and power in gate-level, respectively, as compared to circuit level simulation results.

GATE RESIZING TO REDUCE POWER CONSUMPTION

We study the problem of resizing gates so as to reduce overall power consumption while satisfying a circuit's timing constraints. Polynomial time algorithms for series-parallel and tree circuits are obtained. Gate resizing with multigate modules is shown to be NP-hard. Algorithms that improve upon those presented by Chen and Sarrafzadeh4 for general circuits are also developed.