Novel low power full adder cells in 180nm CMOS technology

2009 ◽  
Author(s):  
Dan Wang ◽  
Maofeng Yang ◽  
Wu Cheng ◽  
Xuguang Guan ◽  
Zhangming Zhu ◽  
...  
Keyword(s):  
Low Power ◽  
Full Adder ◽  
Cmos Technology

scholarly journals Full Adder for Low Power Applications

2020 ◽  
Vol 9 (4) ◽  
pp. 2682-2687
Keyword(s):  
Low Power ◽  
Processing System ◽  
Full Adder ◽  
Cmos Technology ◽  
Fundamental Operation ◽  
Dynamic Power ◽  
Power Delay Product ◽  
Electronic Processing

In an electronic processing system, addition of binary numbers is a fundamental operation. A one bit low power hybrid FA(full adder) is shown in showing performance improvisation by analysis and comparing with other conventional adders. 1 bit low power hybrid full adder is considered as a good way for enhancing the speed of the circuit in comparison with other conventional circuits of full adders. In that analysis paper, one bit low power hybrid FA(full adder) is implemented by EDA tool and the simulation is analysis by using generic 90nm CMOS technology at 5 volts and comparison is done at various voltages with other conventional full adders. For comparing 1 bit low power hybrid full adder with other conventional adders at various parameters such as static and dynamic power usage, delay & pdp (power delay product) are taken into consideration to show that 1 bit low power hybrid full adder is most suitable for various low power applications.

DESIGN AND ANALYSIS OF A NOVEL LOW PDP FULL ADDER CELL

2011 ◽  
Vol 20 (03) ◽  
pp. 439-445 ◽  
Author(s):  
M. H. GHADIRY ◽  
ABU KHARI A'AIN ◽  
M. NADI S.
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Accurate Analysis ◽  
And Performance ◽  
Full Swing ◽  
Driving Capability

This paper, presents a new full-swing low power high performance full adder circuit in CMOS technology. It benefits from a full swing XOR-XNOR module with no feedback transistors, which decreases delay and power consumption. In addition, high driving capability of COUT module and low PDP design of SUM module contribute to more PDP reduction in cascaded mode. In order to have accurate analysis, the new circuit along with several well-known full adders from literature have been modeled and compared with CADENCE. Comparison consists of power consumption, performance, PDP, and area. Results show that there are improvements in both power consumption and performance. This design trades area with low PDP.

scholarly journals Design and Implementation of a Low Power Ternary Full Adder

VLSI Design ◽  
1996 ◽  
Vol 4 (1) ◽  
pp. 75-81 ◽  
Author(s):  
A. Srivastava ◽  
K. Venkatapathy
Keyword(s):  
Low Power ◽  
Dynamic Performance ◽  
Building Blocks ◽  
Full Adder ◽  
Cmos Technology ◽  
Model Parameters ◽  
Cmos Inverter ◽  
Design And Implementation ◽  
Present Design ◽  
Ternary Full Adder

In this work, the design and implementation of a low power ternary full adder are presented in CMOS technology. In a ternary full adder design, the basic building blocks, the positive ternary inverter (PTI) and negative ternary inverter (NTI) are developed using a CMOS inverter and pass transistors. In designs of PTI and NTI, W/L ratios of transistors have been varied for their optimum performance. The ternary full adder and its building blocks have been simulated with SPICE 2G.6 using the MOSIS model parameters. The rise and fall times of PTI show an improvement by a factor of 14 and 4, respectively, and that of the NTI by a factor of nearly 4 and 17, respectively over that of earlier designs implemented in depletion-enhancement CMOS (DECMOS) technology. The noise margins improve by a factor of nearly 2 in PTI and NTI, respectively.The ternary full adder has been fabricated in MOSIS two micron n-well CMOS technology. The full adder and its building blocks, NTI and PTI have been tested experimentally for static and dynamic performance, compared with the SPICE simulated behavior, and close agreement is observed.The ternary-valued logic circuits designed in the present work which do not use depletion mode MOSFETS perform better than that implemented earlier in DECMOS technology. The present design is fully compatible with the current CMOS technology, uses fewer components and dissipates power in the microwatt range.

CNFET Based Low Power Full Adder Circuit for VLSI Applications

2020 ◽  
Vol 10 (3) ◽  
pp. 286-291
Author(s):  
Inamul Hussain ◽  
Saurabh Chaudhury
Keyword(s):  
Low Power ◽  
Building Blocks ◽  
Full Adder ◽  
Cmos Technology ◽  
Vlsi Circuits ◽  
New Device ◽  
Technology Node ◽  
Technological Advances ◽  
Power Delay Product ◽  
Technology Nodes

Background: The Adder is one of the most prominent building blocks in VLSI circuits and systems. Performance of such systems depends mostly on the performance of the adder cell. The scaling down of devices has been the driving force in technological advances. However, in CMOS technology performance of adder cell decreases as technology node scaled down to deep micron regime. Objective: With the growth of research, new device model has been proposed based on carbon nano tube field effect transistor (CNFET). Therefore, there is a need of full adder cell, which performs sufficiently well in CNFET as well as different CMOS technology nodes. Method: A new low power full adder cell has been proposed with a hybrid XOR/XNOR module by using CNFET, which is also compatible for the CMOS technology nodes. The performance of the adder cell is validated with HSPICE simulation in terms of power, delay and power delay product. It is observed that the proposed adder cell performs better than the CMOS, CPL, TGA, 10 T, 14 T, 24 T, HSPC and Hybrid_FA adder cells. The CNFET full adder is designed in 32 nm CNFET model and to appraise its compatibility with Bulk-Si CMOS technology, 90 nm and 32 nm CMOS technology node is used. Conclusion: The proposed adder is very much suitable for both CMOS and CNFET technology based circuits and systems. To validate the result, simulation has been carried out with Synopsis tool. This full adder will definitely dominate other full adder cells at various technology nodes for VLSI applications.

Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques

2020 ◽  
Vol 17 (4) ◽  
pp. 1595-1599
Author(s):  
N. Suresh ◽  
K. Subba Rao ◽  
R. Vassoudevan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Large Scale ◽  
Digital Signal ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Essential Components

Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.

scholarly journals Low-Power CMOS 1-Bit Full Adder using FPGA KIT & DSM Technology

2021 ◽  
Vol 12 (3) ◽  
pp. 5720-5725
Author(s):  
A.S Keerthi Nayani Et. al.
Keyword(s):  
Low Power ◽  
Full Adder ◽  
Cmos Technology ◽  
Ripple Carry Adder ◽  
Xnor Gate ◽  
Low Power Cmos

The aspire of the manuscript be near apply a 14T Full adder unit, so as to make use of little power by means of XOR and XNOR gate . The 4-bit binary adder is constructed in ripple carry adder arrangement. It has been urbanized for little power utilization in falling the no. of transistor. The power utilization be able to abridged by 49% with planned FA difference ate through regular FA. Every one replication outcome contain be approved elsewhere by with 32 nm CMOS technology. The replication outcome of 1-bit adder planned FA shows so as to the planned FA have little power utilization. The hardware accomplishment of 14T FA be agreed with Deep Sub micron Technology

Nonvolatile, Spin-Based, and Low-Power Inexact Full Adder Circuits for Computing-in-Memory Image Processing

SPIN ◽  
2019 ◽  
Vol 09 (03) ◽  
pp. 1950013 ◽  
Author(s):  
Abdolah Amirany ◽  
Ramin Rajaei
Keyword(s):  
Image Processing ◽  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Structural Similarity ◽  
Full Adder ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Approximate Computing ◽  
Static Power

Deep submicron conventional complementary metal oxide semiconductor (CMOS) technology is facing various issues such as high static power consumption due to the increasing leakage currents. In recent years, spin-based technologies like magnetic tunnel junctions (MTJ) have emerged and shown some fascinating features to overcome the aforesaid issues of CMOS technology. The hybrid MTJ/CMOS circuits offer low power consumption, nonvolatility, and high performance. This paper proposes two novel hybrid MTJ/CMOS approximate full-adder circuits (AXMA) for low power approximate computing-in-memory architectures. The proposed AXMAs offer low area, high sensing speed, considerable lower energy consumption, and the lowest power delay product (PDP) than the considered antecedent counterparts. The proposed AXMAs also introduce the advantage of full nonvolatility to the systems. This feature allows the system to be powered off during the idle modes in order to reduce the static power without the need for any retention parts or loss of data. Applications of the proposed AXMAs in digital image processing and their effect on the quality of images considering some relevant metrics like peak signal-to-noise ratio (PSNR) and mean structural similarity (MSSIM) are also investigated using the MATLAB software.

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