A 15-Gbps BiCMOS XNOR gate for fast recognition of COVID-19 in binarized neural networks

The COVID-19 pandemic is spreading around the world causing more than 177 million cases and over 3.8 million deaths according to the European Centre for Disease Prevention and Control. The virus has devastating effects on economies, health, and well-being of worldwide population. Due to the high increase in daily cases, the available number of COVID-19 test kits in under-developed countries is scarce. Hence, it is vital to implement an effective screening method of patients using chest radiography since the equipment already exists. With the presence of automatic detection systems, any abnormalities in chest radiography that characterizes COVID-19 can be identified. Several artificial-intelligence algorithms have been proposed to detect the virus. However, neural networks training is considered to be time-consuming. Since computations in training neural networks are spent on floating-point multiplications, high computational power is required. Multipliers consume the most space and power among all arithmetic operators in deep neural networks. This paper proposes a 15 Gbps high-speed bipolar-complementary-metal-oxide-semiconductor (BiCMOS) exclusive-nor (XNOR) gate to replace multipliers in binarized neural networks. The proposed gate can be implemented on BiCMOS-based field-programmable gate arrays (FPGAs). This will significantly improve the response time in identifying chest abnormalities in CT scans and X-rays.

FPGA Implementation of Threshold-Type Binary Memristor and Its Application in Logic Circuit Design

In this paper, a memristor model based on FPGA (field programmable gate array) is proposed, and the circuit of AND gate and OR gate composed of memristors is built by using this model. Combined with the original NOT gate in FPGA, the NAND gate, NOR gate, XOR gate and the XNOR gate are further realized, and then the adder design is completed. Compared with the traditional gate circuit, this model has obvious advantages in size and non-volatility. At the same time, the establishment of this model will add new research methods and tools for memristor simulation research.

Low-Power CMOS 1-Bit Full Adder using FPGA KIT & DSM Technology

The aspire of the manuscript be near apply a 14T Full adder unit, so as to make use of little power by means of XOR and XNOR gate . The 4-bit binary adder is constructed in ripple carry adder arrangement. It has been urbanized for little power utilization in falling the no. of transistor. The power utilization be able to abridged by 49% with planned FA difference ate through regular FA. Every one replication outcome contain be approved elsewhere by with 32 nm CMOS technology. The replication outcome of 1-bit adder planned FA shows so as to the planned FA have little power utilization. The hardware accomplishment of 14T FA be agreed with Deep Sub micron Technology

Frequency-domain ultrafast passive logic: NOT and XNOR gates

Electronic Boolean logic gates, the foundation of current computation and digital information processing, are reaching final limits in processing power. The primary obstacle is energy consumption which becomes impractically large, > 0.1 fJ/bit per gate, for signal speeds just over several GHz. Unfortunately, current solutions offer either high-speed operation or low-energy consumption. We propose a design for Boolean logic that can achieve both simultaneously (high speed and low consumption), here demonstrated for NOT and XNOR gates. Our method works by passively modifying the phase relationships among the different frequencies of an input data signal to redistribute its energy into the desired logical output pattern. We experimentally demonstrate a passive NOT gate with an energy dissipation of ~1 fJ/bit at 640 Gb/s and use it as a building block for an XNOR gate. This approach is applicable to any system that can propagate coherent waves, such as electromagnetic, acoustic, plasmonic, mechanical, or quantum.

Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.