Timing characterization and layout of a low power differential C2MOS flip flop in 0.35μm technology

2008 ◽  
Author(s):  
A. Dendouga ◽  
N. Bouguechal ◽  
S. Barra ◽  
O. Manck
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Power Differential

scholarly journals Low-Power Differential Input to Single-Ended Output GaN RF-DAC for RF-Signal Generation

2021 ◽  
pp. 1-1
Author(s):  
Markus Weiss ◽  
Christian Friesicke ◽  
Rudiger Quay ◽  
Oliver Ambacher
Keyword(s):  
Low Power ◽  
Signal Generation ◽  
Power Differential ◽  
Differential Input ◽  
Rf Signal

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement

2007 ◽  
Author(s):  
T. Baumann ◽  
J. Berthold ◽  
T. Niedermeier ◽  
T. Schoenauer ◽  
J. Dienstuhl ◽  
...  
Keyword(s):  
Low Power ◽  
Performance Improvement ◽  
Flip Flop

High-performance and low-power conditional discharge flip-flop

2004 ◽  
Vol 12 (5) ◽  
pp. 477-484 ◽  
Author(s):  
Peiyi Zhao ◽  
T.K. Darwish ◽  
M.A. Bayoumi
Keyword(s):  
Low Power ◽  
High Performance ◽  
Flip Flop ◽  
Conditional Discharge

Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop

2021 ◽  
Author(s):  
Yugal Maheshwari ◽  
Kleber Stangherlin ◽  
Derek Wright ◽  
Manoj Sachdev
Keyword(s):  
Low Power ◽  
Single Phase ◽  
Low Energy ◽  
Flip Flop ◽  
Ultra Low Power

scholarly journals Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

2019 ◽  
Vol 54 (2) ◽  
pp. 550-559 ◽  
Author(s):  
Yunpeng Cai ◽  
Anand Savanth ◽  
Pranay Prabhat ◽  
James Myers ◽  
Alex S. Weddell ◽  
...  
Keyword(s):  
Low Power ◽  
Single Phase ◽  
Flip Flop ◽  
Ultra Low Power
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