A Low-Power RC Oscillator with Offset and Path Delay Cancellation

2021 ◽  
Author(s):  
Yueduo Liu ◽  
Zihao Zhu ◽  
Rongxin Bao ◽  
Shiheng Yang ◽  
Jiaxin Liu ◽  
...  
Keyword(s):  
Low Power ◽  
Path Delay

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

Error-resilient low-power DSP via path-delay shaping

2011 ◽  
Author(s):  
Paul Whatmough ◽  
Shidhartha Das ◽  
David Bull ◽  
Izzat Darwazeh
Keyword(s):  
Low Power ◽  
Path Delay ◽  
Error Resilient

scholarly journals A new low-power butterfly unit for single-path delay feedback FFT architectures

2013 ◽  
Vol 10 (24) ◽  
pp. 20130640-20130640
Author(s):  
Seung-Won Yang ◽  
Jong-Yeol Lee
Keyword(s):  
Low Power ◽  
Path Delay ◽  
Single Path

scholarly journals VLSI Architecture of High Performance Multiplier for High Speed Applications

2020 ◽  
Vol 9 (3) ◽  
pp. 442-445
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Vlsi Architecture ◽  
Digital Signal ◽  
Full Adder ◽  
Vital Role ◽  
Path Delay

In the application of digital signal process multipliers play a vital role. With advances in technology, several researchers have tried and try to design multipliers which supply high speed, low power consumption, regularity of layout and thus less space or maybe combination of them in one multiplier factor. Thus, Compact VLSI design for four bit multiplier factor is planned during this paper that is appropriate for low power and high speed applications. Multiplier factor with high performance is achieved through the novel style of hybrid single bit full adder and Dadda algorithmic rule. The important path delay and power consumption of the planned multiplier factor square measure reduced by 65.9% and 24.5% severally when put next with existing multipliers. The planned multiplier factor is synthesized exploitation CADENCE five.1.0 EDA tool and simulated exploitation spectre virtuoso.

scholarly journals Path Delay Optimized Booth Radix-8 Architecture

2019 ◽  
Vol 8 (2S5) ◽  
pp. 235-237
Keyword(s):  
Low Power ◽  
Path Delay ◽  
General Power

In this paper, a quick and low power marked MAC Unit is proposed with reconfigurable Modified stall calculation (MBE). The proposed engineering depends on adjusted corner radix-8 with consolidated 2's supplement and MUX units with a low basic way postponement and low equipment multifaceted nature. Here corner-based methodology for incomplete items ages and Tree based methodology for halfway items decrease in increases. The new decreases design the equipment intricacy of the summation arrange utilizing consolidated swell convey viper and convey look forward (CLA), along these lines lessens the general power and multifaceted nature. Expanding the speed of activity can be broadened utilizing marked corner radix-8 based MAC unit with noteworthy execution enhancement. We can stall augmentation into two sections, incomplete item age and halfway item amassing. Accelerating augmentation, hence, must point (I) accelerating fractional item age, (ii) decreasing the quantity of incomplete items, (iii) accelerating halfway item summation or (iv) a combination of the above.

Low Power Test Generation for Path Delay Faults

2005 ◽  
Vol 1 (2) ◽  
pp. 194-205
Author(s):  
M. M. Vaseekar Kumar ◽  
S. Tragoudas
Keyword(s):  
Low Power ◽  
Test Generation ◽  
Delay Faults ◽  
Path Delay ◽  
Path Delay Faults ◽  
Power Test ◽  
Low Power Test

Hardware-Efficient Bartlett Spectral Density Estimator Based on Optimized R22FFT Processor Using CCSSI Method

2020 ◽  
pp. 2150023
Author(s):  
Abdolvahab Khalili Sadaghiani ◽  
Samad Sheikhaei
Keyword(s):  
Spectral Density ◽  
Low Power ◽  
Performance Comparison ◽  
Density Estimator ◽  
Path Delay ◽  
Fft Processor ◽  
Power Spectral ◽  
Coordinate Rotation ◽  
Psd Estimation ◽  
Single Path

This paper offers a novel, low-power, hardware-efficient, yet high-frequency architecture for a power spectral density (PSD) estimator, based on the Bartlett method, for low-power biomedical applications. The Bartlett method is a nonparametric method for PSD estimation. The proposed architecture operates based on a modified multiplierless 64-point optimized radix-22 single-path delay feedback (R22SDF) FFT processor. To obtain the final result, it also uses modified safe-scaling in a way that removes the need to use several extra hardware units. It takes advantage of combined coefficient selection and shift-and-add implementation (CCSSI) for computing twiddle factors which is a new algorithm based on digital computer coordinate rotation (CORDIC) for generating trigonometric values. The proposed method has the capability of operating on short word lengths (WLs). Artix-7 is the FPGA used in this research and Verilog is the language used for hardware design. For 8-bit WL and 244-mW power, a frequency of 286 MHz has been achieved. Several vital signals are used for performance comparison of the proposed technique with state-of-the-art designs.

Sign in / Sign up

Export Citation Format

Share Document