Scaling the high-performance double-gate SOI MOSFET down to the 32 nm technology node with SiO/sub 2/-based gate stacks

Author(s):  
N. Barin ◽  
M. Braccioli ◽  
C. Fiegna ◽  
E. Sangiorgi
Author(s):  
Enrico Sangiorgi ◽  
Nicola Barin ◽  
Marco Braccioli ◽  
Claudio Fiegna

2018 ◽  
Vol 7 (2.8) ◽  
pp. 191
Author(s):  
Arjimand Ashaf ◽  
Manisha Tyagi ◽  
Prashant Mani

In this paper, we are presenting a rigorous study about SOI MOSFET devices development. The development of SOI devices based on gate structure from single gate to surround gate is presented in this paper. We compared the various electrical characteristics between Single gate, double gate, and bulk and also discussed the device modeling based on surround gate structure.


2010 ◽  
Vol 7 (5) ◽  
pp. 371-376 ◽  
Author(s):  
Farzan Jazayeri ◽  
Farshid Raissi ◽  
Behjat Forouzandeh

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