Modeling and simulation of microcode Memory Built In Self Test architecture for embedded memories

2007 International Symposium on Communications and Information Technologies ◽

10.1109/iscit.2007.4392000 ◽

2007 ◽

Author(s):

Nor Zaidi Haron ◽

Siti Aisah Mat Junos ◽

Amir Shah Abdul Aziz

Keyword(s):

Modeling And Simulation ◽

Self Test ◽

Built In Self Test ◽

Embedded Memories ◽

Test Architecture

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Modeling and simulation of finite state machine Memory Built-in Self Test architecture for embedded memories

2007 Asia-Pacific Conference on Applied Electromagnetics ◽

10.1109/apace.2007.4603901 ◽

2007 ◽

Author(s):

Nor Zaidi Haron ◽

Siti Aisah Mat Junos ◽

Abdul Hadi Abdul Razak ◽

Mohd. Yamani Idna Idris

Keyword(s):

Modeling And Simulation ◽

Finite State Machine ◽

State Machine ◽

Finite State ◽

Self Test ◽

Built In Self Test ◽

Machine Memory ◽

Embedded Memories ◽

Test Architecture

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IBIST/sup TM/ (interconnect built-in self-test) architecture and methodology for pci express: intel's next-generation test and validation methodology for performance IO

International Test Conference, 2003. Proceedings. ITC 2003. ◽

10.1109/test.2003.1270909 ◽

2004 ◽

Author(s):

J.J. Nejedlo

Keyword(s):

Next Generation ◽

Pci Express ◽

Self Test ◽

Built In Self Test ◽

Test Architecture ◽

Generation Test

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Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture

2011 Design, Automation & Test in Europe ◽

10.1109/date.2011.5763109 ◽

2011 ◽

Author(s):

A Strano ◽

C Gómez ◽

D Ludovici ◽

M Favalli ◽

M E Gómez ◽

...

Keyword(s):

Network On Chip ◽

Structural Redundancy ◽

Self Test ◽

Built In Self Test ◽

On Chip ◽

Test Architecture

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Configurable Built-In Self-Test Architecture for Automated Testing of a Dual-Axis Solar Tracker

10.1109/eeeic/icpseurope51590.2021.9584768 ◽

2021 ◽

Author(s):

Raul Rotar ◽

Sorin Liviu Jurj

Keyword(s):

Automated Testing ◽

Solar Tracker ◽

Self Test ◽

Built In Self Test ◽

Test Architecture

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Semiconductor manufacturing process monitoring using built-in self-test for embedded memories

Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270) ◽

10.1109/test.1998.743277 ◽

2002 ◽

Author(s):

I. Schanstra ◽

D. Lukita ◽

A.J. van de Goor ◽

K. Veelenturf ◽

P.J. van Wijnen

Keyword(s):

Process Monitoring ◽

Manufacturing Process ◽

Semiconductor Manufacturing ◽

Self Test ◽

Built In Self Test ◽

Embedded Memories

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Design of Modified March-C Algorithm and Built-in self-test architecture for Memories

3C Tecnología_Glosas de innovación aplicadas a la pyme ◽

10.17993/3ctecno.2020.specialissue4.219-229 ◽

2020 ◽

pp. 219-229

Author(s):

G. Karthy ◽

P. Sivakumar

Keyword(s):

Self Test ◽

Built In Self Test ◽

Test Architecture

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A Memory Built-In Self-Test Architecture for Memories Different in Size

2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis ◽

10.1109/cas-ictd.2009.4960752 ◽

2009 ◽

Author(s):

Quan-Lin Rao ◽

Chun He ◽

Yu-Ming Jia

Keyword(s):

Self Test ◽

Built In Self Test ◽

Test Architecture

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Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC

10.1109/isocc53507.2021.9613959 ◽

2021 ◽

Author(s):

Donghyun Han ◽

Youngkwang Lee ◽

Sooryeong Lee ◽

Sungho Kang

Keyword(s):

3D Ic ◽

Self Test ◽

Built In Self Test ◽

Test Architecture

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Arithmetic module-based built-in self test architecture for two-pattern testing

IET Computers & Digital Techniques ◽

10.1049/iet-cdt.2010.0061 ◽

2012 ◽

Vol 6 (4) ◽

pp. 195

Author(s):

I. Voyiatzis ◽

C. Efstathiou ◽

H. Antonopoulou ◽

A. Milidonis

Keyword(s):

Self Test ◽

Built In Self Test ◽

Test Architecture

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Designing built-in self-test circuits for embedded memories test

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) ◽

10.1109/apasic.2000.896971 ◽

2002 ◽

Author(s):

Sanghun Park ◽

Kijong Lee ◽

Changbum Im ◽

Nami Kwak ◽

Kihyun Kim ◽

...

Keyword(s):

Self Test ◽

Built In Self Test ◽

Embedded Memories

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