32 Bit re-configurable RISC processor design and implementation for BETA ISA with inbuilt matrix multiplier

Pipelining is the concept of overlapping of multiple instructions to perform their operations to optimize the time and ability of hardware units. This paper presents the design and implementation of 6 stage pipelined architecture for High performance 64-bit Microprocessor without Interlocked Pipeline Stages (MIPS) based Reduced Instruction set computing (RISC) processor. In this work, combining efforts of pre-fetching unit, forwarding unit, Branch and Jump predicting unit, Hazard unit are used to reduce the hazards. Low power unit is used to minimize the power. Cache Memories, other devices and especially balancing pipeline stages optimize the Speed in this work. DDR4 SDRAM (Double Data Rate type4 Synchronous Dynamic Random Access Memory) controller is employed in this pipeline to achieve high-speed data transfers and to manage the entire system efficiently. Low power, Low delay Flip flops are used in pipeline registers that implicitly enhance the performance of the system. The proposed method provides better results compared to the existing models. The simulation and synthesis results of the proposed Architecture are evaluated by Xilinx 14.7 software and supporting graphs are plotted through MATLAB tool

Download Full-text

AnnikaCore: RISC-V Architecture Processor Design and Implementation for IoT

10.1109/asid52932.2021.9651690 ◽

2021 ◽

Author(s):

Yunrui Zhang ◽

Zichao Guo ◽

Jian Li ◽

Fan Cai ◽

Jianyang Zhou

Keyword(s):

Processor Design ◽

Design And Implementation

Download Full-text

A single clock cycle MIPS RISC processor design using VHDL

ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575) ◽

10.1109/smelec.2002.1217806 ◽

2004 ◽

Cited By ~ 6

Author(s):

M.B.I. Reaz ◽

M.S. Islam ◽

M.S. Sulaiman

Keyword(s):

Clock Cycle ◽

Processor Design ◽

Risc Processor

Download Full-text

Design and Implementation of Synthesizable 32-bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL

Nepal Journal of Science and Technology ◽

10.3126/njst.v15i1.12021 ◽

2015 ◽

Vol 15 (1) ◽

pp. 81-88 ◽

Cited By ~ 1

Author(s):

Bikash Poduel ◽

Prasanna Kansakar ◽

Sujit R. Chhetri ◽

Shashidhar Ram Joshi

Keyword(s):

High Performance ◽

Control Unit ◽

Verilog Hdl ◽

Design And Implementation ◽

Risc Processor ◽

Data Memory ◽

Memory Register ◽

Reduced Instruction Set Computer ◽

Instruction Memory ◽

Harvard Architecture

This paper is delineating the design and implementation of high performance, synthesizable 32-bit pipelined Reduced Instruction Set Computer (RISC) Core. The design of the Harvard Architecture based 32-bit RISC Core involves design of 32-bit Data-path Unit, Control Unit, 32-bit Instruction Memory, 32-bit Data Memory, Register file with each register of size 32 bit. The processor is divided into Fetch, Decode, Execute and Write Back block in order to implement a four-stage pipeline. A 2*16 LCD is connected to the processor IO block to show the instruction execution sequence for demonstration in FPGA. The RISC Core is designed using Verilog HDL and VHDL and is tested in ISIM Simulator. The implementation of the processor is done in a Spartan 3E Starter Board using Xilinx ISE 14.7. All of the instructions incorporated with the processor have been tested successfully both in simulation and hardware implementation in FPGA.DOI: http://dx.doi.org/10.3126/njst.v15i1.12021 Nepal Journal of Science and TechnologyVol. 15, No.1 (2014) 81-88

Download Full-text