Prefetching across a shared memory tree within a Network-on-Chip architecture

2013 International Symposium on System on Chip (SoC) ◽

10.1109/issoc.2013.6675268 ◽

2013 ◽

Author(s):

Jamie Garside ◽

Neil C. Audsley

Keyword(s):

Shared Memory ◽

Network On Chip ◽

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Response time analysis of dataflow applications on a many-core processor with shared-memory and network-on-chip

Proceedings of the 27th International Conference on Real-Time Networks and Systems - RTNS '19 ◽

10.1145/3356401.3356416 ◽

2019 ◽

Author(s):

Amaury Graillat ◽

Claire Maiza ◽

Matthieu Moy ◽

Pascal Raymond ◽

Benoît Dupont de Dinechin

Keyword(s):

Response Time ◽

Shared Memory ◽

Network On Chip ◽

Response Time Analysis ◽

Time Analysis ◽

On Chip ◽

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A Network-on-Chip based homogeneous many-core Digital Signal Processor framework with distributed shared memory

Information Technology and Applications ◽

10.1201/b18284-73 ◽

2015 ◽

pp. 365-369

Author(s):

Qinhong Zhang ◽

Fang Wang ◽

Zhaolin Li

Keyword(s):

Shared Memory ◽

Digital Signal Processor ◽

Distributed Shared Memory ◽

Digital Signal ◽

Network On Chip ◽

On Chip ◽

Many Core ◽

Signal Processor

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Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors

10.4995/thesis/10251/35325 ◽

2014 ◽

Author(s):

Mario Lodde

Keyword(s):

Shared Memory ◽

High Performance ◽

Chip Multiprocessors ◽

Network On Chip ◽

Chip Design ◽

Memory Chip ◽

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Real Time Network on Chip (NOC) Architecture with CDMA Techniques with Audio Decoders

Oct. 17-19, 2017 Dubai (UAE) ◽

10.15242/dirpub.dir1017020 ◽

2018 ◽

Keyword(s):

Real Time ◽

Network On Chip ◽

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A congestion-aware routing algorithm for simplified mesh-of-tree architecture in network-on-chip designs

Artificial Intelligence and Industrial Application ◽

10.2495/aiia140551 ◽

2015 ◽

Author(s):

J. Fang ◽

L. Yu ◽

Z. Y. Leng

Keyword(s):

Routing Algorithm ◽

Network On Chip ◽

Tree Architecture ◽

On Chip ◽

Congestion Aware

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VLSI Design Of Low Energy Modeling For Network On Chip (NoC) Applications

i-manager’s Journal on Electronics Engineering ◽

10.26634/jele.5.1.3320 ◽

2014 ◽

Vol 5 (1) ◽

pp. 27-32

Author(s):

Jeeva Anusha ◽

◽

V. Thrimurthulu ◽

Keyword(s):

Vlsi Design ◽

Network On Chip ◽

Energy Modeling ◽

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Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

JOURNAL OF ELECTRONICS INFORMATION TECHNOLOGY ◽

10.3724/sp.j.1146.2012.00654 ◽

2014 ◽

Vol 35 (2) ◽

pp. 341-346

Author(s):

Xiao-fu Zheng ◽

Hua-xi Gu ◽

Yin-tang Yang ◽

Zhong-fan Huang

Keyword(s):

Network On Chip ◽

Low Latency ◽

Router Architecture ◽

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Example Antenna and Link Performance for Wireless Network on Chip Applications

12th European Conference on Antennas and Propagation (EuCAP 2018) ◽

10.1049/cp.2018.0956 ◽

2018 ◽

Author(s):

W. Rayess ◽

D.W. Matolak

Keyword(s):

Wireless Network ◽

Network On Chip ◽

Link Performance ◽

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An optimized path-setup method for mesh based Optical Network on Chip

2015 14th International Conference on Optical Communications and Networks (ICOCN) ◽

10.1109/icocn.2015.7203619 ◽

2015 ◽

Author(s):

Wei Tan ◽

Bowen Zhang ◽

Huaxi Gu ◽

Zheng Chen

Keyword(s):

Optical Network ◽

Network On Chip ◽

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A Novel Scheme to Map Convolutional Networks to Network-on-Chip with Computing-In-Memory Nodes

2020 International SoC Design Conference (ISOCC) ◽

10.1109/isocc50952.2020.9332940 ◽

2020 ◽

Author(s):

Jiayi Liu ◽

Kejie Huang

Keyword(s):

Network On Chip ◽

Convolutional Networks ◽

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