Thick-Strained-Si/SiGe CMOS Technology with Selective-Epitaxial-Si Shallow-Trench Isolation (SES-STI)

Author(s):  
M. Miyamoto ◽  
N. Sugii ◽  
Y. Yoshida ◽  
Y. Hoshino ◽  
Y. Kimura ◽  
...  
2007 ◽  
Vol 54 (9) ◽  
pp. 2460-2465 ◽  
Author(s):  
M.. Miyamoto ◽  
N.. Sugii ◽  
Y.. Hoshino ◽  
Y.. Yoshida ◽  
M.. Kondo ◽  
...  

1999 ◽  
Vol 567 ◽  
Author(s):  
Udo Schwalke ◽  
Christian Gruensfelder ◽  
Alexander Gschwandtner ◽  
Gudrun Innertsberger ◽  
Martin Kerber

ABSTRACTWe have realized direct-tunneling gate oxide (1.6nm) NMOS and PMOS transistors by means of through-the-gate-implantation in a comer parasitics-free shallow-trench-isolation CMOS technology. In order to take full advantage of in-situ cluster-tool processing and to preserve initial wafer-surface quality, the essential part of the MOS gate is fabricated prior to device isolation and through-the-gate-implantation is utilized for well- and channel doping. In addition, a fully-reinforced-gate-oxide-perimeter is provided and trench comer parasitics are eliminated by the advanced process architecture EXTIGATE without increasing process complexity.


1998 ◽  
Author(s):  
U. Schwalke ◽  
M. Fuldner ◽  
W. Zatsch ◽  
K. Bothe ◽  
D. Hadawi ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document