Improved implementation of a modified Discrete Cosine Transform on low-cost FPGA

2010 ◽  
Author(s):  
S. Belkouch ◽  
M. El Aakif ◽  
A. Ait Ouahman ◽  
M. M. Hassani
Keyword(s):  
Discrete Cosine Transform ◽  
Low Cost ◽  
Cosine Transform ◽  
Modified Discrete Cosine Transform

scholarly journals Superwideband Bandwidth Extension Using Normalized MDCT Coefficients for Scalable Speech and Audio Coding

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Young Han Lee ◽  
Seung Ho Choi
Keyword(s):  
Discrete Cosine Transform ◽  
Audio Coding ◽  
Bandwidth Extension ◽  
Spectral Parameters ◽  
Cosine Transform ◽  
Modified Discrete Cosine Transform ◽  
Audio Codec ◽  
Speech And Audio Coding

A bandwidth extension (BWE) algorithm from wideband to superwideband (SWB) is proposed for a scalable speech/audio codec that uses modified discrete cosine transform (MDCT) coefficients as spectral parameters. The superwideband is first split into several subbands that are represented as gain parameters and normalized MDCT coefficients in the proposed BWE algorithm. We then estimate normalized MDCT coefficients of the wideband to be fetched for the superwideband and quantize the fetch indices. After that, we quantize gain parameters by using relative ratios between adjacent subbands. The proposed BWE algorithm is embedded into a standard superwideband codec, the SWB extension of G.729.1 Annex E, and its bitrate and quality are compared with those of the BWE algorithm already employed in the standard superwideband codec. It is shown from the comparison that the proposed BWE algorithm relatively reduces the bitrate by around 19% with better quality, compared to the BWE algorithm in the SWB extension of G.729.1 Annex E.

Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs

2022 ◽  
Vol 15 (3) ◽  
pp. 1-25
Author(s):  
S. Rasoul Faraji ◽  
Pierre Abillama ◽  
Kia Bazargan
Keyword(s):  
Discrete Cosine Transform ◽  
Video Processing ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Logic Gates ◽  
Cosine Transform ◽  
Real Time Processing ◽  
Coefficient Multiplier ◽  
Encoding Method

Multipliers are used in virtually all Digital Signal Processing (DSP) applications such as image and video processing. Multiplier efficiency has a direct impact on the overall performance of such applications, especially when real-time processing is needed, as in 4K video processing, or where hardware resources are limited, as in mobile and IoT devices. We propose a novel, low-cost, low energy, and high-speed approximate constant coefficient multiplier (CCM) using a hybrid binary-unary encoding method. The proposed method implements a CCM using simple routing networks with no logic gates in the unary domain, which results in more efficient multipliers compared to Xilinx LogiCORE IP CCMs and table-based KCM CCMs (Flopoco) on average. We evaluate the proposed multipliers on 2-D discrete cosine transform algorithm as a common DSP module. Post-routing FPGA results show that the proposed multipliers can improve the {area, area × delay, power consumption, and energy-delay product} of a 2-D discrete cosine transform on average by {30%, 33%, 30%, 31%}. Moreover, the throughput of the proposed 2-D discrete cosine transform is on average 5% more than that of the binary architecture implemented using table-based KCM CCMs. We will show that our method has fewer routability issues compared to binary implementations when implementing a DCT core.

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