Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs

Multipliers are used in virtually all Digital Signal Processing (DSP) applications such as image and video processing. Multiplier efficiency has a direct impact on the overall performance of such applications, especially when real-time processing is needed, as in 4K video processing, or where hardware resources are limited, as in mobile and IoT devices. We propose a novel, low-cost, low energy, and high-speed approximate constant coefficient multiplier (CCM) using a hybrid binary-unary encoding method. The proposed method implements a CCM using simple routing networks with no logic gates in the unary domain, which results in more efficient multipliers compared to Xilinx LogiCORE IP CCMs and table-based KCM CCMs (Flopoco) on average. We evaluate the proposed multipliers on 2-D discrete cosine transform algorithm as a common DSP module. Post-routing FPGA results show that the proposed multipliers can improve the {area, area × delay, power consumption, and energy-delay product} of a 2-D discrete cosine transform on average by {30%, 33%, 30%, 31%}. Moreover, the throughput of the proposed 2-D discrete cosine transform is on average 5% more than that of the binary architecture implemented using table-based KCM CCMs. We will show that our method has fewer routability issues compared to binary implementations when implementing a DCT core.

Symmetries in reversible programming: from symmetric rig groupoids to reversible programming languages

The Pi family of reversible programming languages for boolean circuits is presented as a syntax of combinators witnessing type isomorphisms of algebraic data types. In this paper, we give a denotational semantics for this language, using weak groupoids à la Homotopy Type Theory, and show how to derive an equational theory for it, presented by 2-combinators witnessing equivalences of type isomorphisms. We establish a correspondence between the syntactic groupoid of the language and a formally presented univalent subuniverse of finite types. The correspondence relates 1-combinators to 1-paths, and 2-combinators to 2-paths in the universe, which is shown to be sound and complete for both levels, forming an equivalence of groupoids. We use this to establish a Curry-Howard-Lambek correspondence between Reversible Logic, Reversible Programming Languages, and Symmetric Rig Groupoids, by showing that the syntax of Pi is presented by the free symmetric rig groupoid, given by finite sets and bijections. Using the formalisation of our results, we perform normalisation-by-evaluation, verification and synthesis of reversible logic gates, motivated by examples from quantum computing. We also show how to reason about and transfer theorems between different representations of reversible circuits.

Nonlinear co-generation of graphene plasmons for optoelectronic logic gates

Surface plasmons in graphene provide a compelling strategy for advanced photonic technologies thanks to their tight confinement, fast response and tunability. Recent advances in the field of all-optical generation of graphene’s plasmons in planar waveguides offer a promising method for high-speed signal processing in nanoscale integrated optoelectronic devices. Here, we use two counter propagating frequency combs with temporally synchronized pulses to demonstrate deterministic all-optical generation and electrical control of multiple plasmon polaritons, excited via difference frequency generation (DFG). Electrical tuning of a hybrid graphene-fiber device offers a precise control over the DFG phase-matching, leading to tunable responses of the graphene’s plasmons at different frequencies and provides a powerful tool for high-speed logic operations. Our results offer new insights for plasmonics on hybrid photonic devices based on layered materials and pave the way to high-speed integrated optoelectronic computing circuits.

Terminal Deoxynucleotidyl Transferase Extension-Dominated In Situ Signal Attenuation-Free Electrochemical Platform and Its Logic Gate Manipulation

Signal generation of traditional electrochemical biosensors suffers from the random diffusion of electroactive probes in a electrolyte solution, which is accompanied by poor reaction kinetics and low signal stability from complex biological systems. Herein, a novel circuit system with autonomous compensation solution ohmic drop (noted as “fast-scan cyclic voltammetry (FSCV)”) is developed to solve the above problems, and employed to achieve terminal deoxynucleotide transferase (TdT) and its small molecule inhibitor analysis. At first, a typical TdT-mediated catalytic polymerization in the conditions of original DNA, deoxythymine triphosphate (dTTP) and Hg2+ is applied for the electrode assembly. The novel electrochemical method can provide some unattenuated signals due to in-situ Hg redox reaction, thus improving reaction kinetics and signal stability. This approach is mainly dependent on TdT-mediated reaction, so it can be applied properly for TdT investigation, and a detection limit of 0.067 U/mL (S/N=3) is achieved successfully. More interesting, we also mimic the function of TdT-related signal communication in various logic gates such as YES, NOT, AND, N-IMPLY, and AND-AND-N-IMPLY cascade circuit. This study provides a new method for the detection of TdT biomarkers in many types of diseases and the construction of a signal attenuation-free logic gate.

A Monolithic Stochastic Computing Architecture for Energy and Area Efficient Arithmetic

As the energy and hardware investments necessary for conventional high-precision digital computing continues to explode in the emerging era of artificial intelligence, deep learning, and Big-data [1-4], a change in paradigm that can trade precision for energy and resource efficiency is being sought for many computing applications. Stochastic computing (SC) is an attractive alternative since unlike digital computers, which require many logic gates and a high transistor volume to perform basic arithmetic operations such as addition, subtraction, multiplication, sorting etc., SC can implement the same using simple logic gates [5, 6]. While it is possible to accelerate SC using traditional silicon complementary metal oxide semiconductor (CMOS) [7, 8] technology, the need for extensive hardware investment to generate stochastic bits (s-bit), the fundamental computing primitive for SC, makes it less attractive. Memristor [9-11] and spin-based devices [12-15] offer natural randomness but depend on hybrid designs involving CMOS peripherals for accelerating SC, which increases area and energy burden. Here we overcome the limitations of existing and emerging technologies and experimentally demonstrate a standalone SC architecture embedded in memory based on two-dimensional (2D) memtransistors. Our monolithic and non-von Neumann SC architecture consumes a miniscule amount of energy < 1 nano Joules for s-bit generation and to perform arithmetic operations and occupy small hardware footprint highlighting the benefits of SC.

An application-specific image processing array based on WSe2 transistors with electrically switchable logic functions

With the rapid development of artificial intelligence, parallel image processing is becoming an increasingly important ability of computing hardware. To meet the requirements of various image processing tasks, the basic pixel processing unit contains multiple functional logic gates and a multiplexer, which leads to notable circuit redundancy. The pixel processing unit retains a large optimizing space to solve the area redundancy issues in parallel computing. Here, we demonstrate a pixel processing unit based on a single WSe2 transistor that has multiple logic functions (AND and XNOR) that are electrically switchable. We further integrate these pixel processing units into a low transistor-consumption image processing array, where both image intersection and image comparison tasks can be performed. Owing to the same image processing power, the consumption of transistors in our image processing unit is less than 16% of traditional circuits.

Alternative method of implementation of all-optical NOR and NAND gates using quantum-dot semiconductor optical amplifiers in non-interferometer structure

Present communication deals with the design and analysis of all-optical NOR and NAND gates using Quantum dot Semiconductor Optical Amplifiers (QDSOA). The design uses no interferometer structure but cross gain modulation is utilized for operation. The structures are simple and simulations at a rate of 1 Tb/s are processed. For unsaturated gain 30 dB, the logic gates show high values of ER (29.82 dB, 16.93 dB), CR (29.6 dB, 21.33 dB), and Q (25.4 dB, 13.2 dB). This ensures practical feasibility and high quality of the proposed gates.