Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model

2016 ◽  
Author(s):  
Jeongwoo Heo ◽  
Taewhan Kim
Keyword(s):  
Timing Analysis ◽  
Flip Flop ◽  
Timing Model

ACCURATE GATE DELAY EXTRACTION FOR TIMING ANALYSIS OF BODY-BIASED CIRCUITS

2013 ◽  
Vol 22 (08) ◽  
pp. 1350072 ◽  
Author(s):  
DONKYU BAEK ◽  
INSUP SHIN ◽  
YOUNGSOO SHIN
Keyword(s):  
Bias Voltage ◽  
Timing Analysis ◽  
Average Error ◽  
Gate Delay ◽  
Timing Model ◽  
New Process ◽  
Delay Extraction ◽  
Circuit Technique ◽  
Static Body ◽  
Body Bias

Static body biasing is a circuit technique in which bias voltage is selected from more than one available voltage after manufacturing. It allows circuits to be designed at more favorable process corners; but effective application requires gate delays to be available for the new process corners, without the expense of re-characterizing individual gates. We show that the new delay of a gate (when body bias is applied) can be extrapolated from its old delay without body bias together with old and new delays of a few reference gates. Output transition time, which is another component of gate timing model, is extrapolated in a similar manner. Experiments with an industrial 32-nm gate library show that the average error in the new gate delays is less than 4.3%.

SAMPLING CORRELATION SOURCES FOR TIMING YIELD ANALYSIS OF SEQUENTIAL CIRCUITS WITH CLOCK NETWORKS

2011 ◽  
Vol 20 (08) ◽  
pp. 1547-1569
Author(s):  
LEE-EUN YU ◽  
CHANGSIK SHIN ◽  
SEUNGWHUN PAIK ◽  
JING-JIA LIOU ◽  
YOUNGSOO SHIN
Keyword(s):  
Timing Analysis ◽  
Computation Time ◽  
Process Variations ◽  
Branch Points ◽  
Static Timing Analysis ◽  
Flip Flop ◽  
Clock Networks ◽  
Yield Analysis ◽  
Clock Network ◽  
Discrete Random Variables

Analyzing timing yield under process variations is difficult because of the presence of correlations. Reconvergent fan-out nodes (RFONs) within combinational subcircuits are a major source of topological correlation. We identify two more sources of topological correlation in clocked sequential circuit: sequential RFONs, which are nodes within a clock network where the clock paths to more than one flip-flop branch out; and sequential branch-points, which are nodes within a combinational block where combinational paths to more than one capturing flip-flop branch out. Dealing with all sources of correlation is unacceptably complicated, and we therefore show how to sample a handful of correlation sources without sacrificing significant accuracy in the yield. A further reduction in computation time can be obtained by sampling only those nodes that are likely to affect the yield. These techniques are applied to yield analysis using statistical static timing analysis based on discrete random variables and also to yield analysis based on Monte Carlo simulation; the accuracy and efficiency of both methods are assessed using example circuits. The sequential RFONs suggest that timing yield may be improved by optimizing the clock network, and we address this possibility.

Concurrent multi-mode timing model generation for hierarchical timing analysis

2016 ◽  
Author(s):  
Naresh Kumar ◽  
Parag Bhatnagar ◽  
N. K. Agarwal ◽  
P. S. Bhatnagar
Keyword(s):  
Timing Analysis ◽  
Model Generation ◽  
Timing Model ◽  
Hierarchical Timing ◽  
Multi Mode
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