A Scaling-Friendly Low-Power Small-Area $\Delta\Sigma$ ADC With VCO-Based Integrator and Intrinsic Mismatch Shaping Capability

2015 ◽  
Vol 5 (4) ◽  
pp. 561-573 ◽  
Author(s):  
Kyoungtae Lee ◽  
Yeonam Yoon ◽  
Nan Sun
Keyword(s):  
Low Power ◽  
Small Area ◽  
Area Formula ◽  
Delta Sigma ◽  
Mismatch Shaping

scholarly journals A Small-Area, Low-Power Delta-Sigma DAC Applied to a Power-Specific Chip

2021 ◽  
Vol 2021 ◽  
pp. 1-8
Author(s):  
Peng Li ◽  
Wei Xi ◽  
Xiangjun Zeng ◽  
Xiaobo Li ◽  
Dandan Zheng
Keyword(s):  
Low Power ◽  
Small Area ◽  
Dynamic Range ◽  
Cmos Process ◽  
Delta Sigma ◽  
Band Filter ◽  
Power Line Carrier ◽  
Power Line Carrier Communication ◽  
Carrier Communication ◽  
Oversampling Ratio

This paper introduces a small-area, low-power delta-sigma DAC that can support power line carrier communication. In order to achieve the oversampling ratio of 128, a three-stage cascaded half-band filter is utilized. An optimized sturdy MASH Δ Σ modulator was used to avoid instability caused by high-order shaping and reduce the area at the same time. The postanalog reconstruction includes a switched-capacitor DAC (SC DAC) and a 4-tap FIR/IIR hybrid filter, which not only meets the requirements of low power but also promotes the out-of-band SNR. The final chip is fabricated in a 55 nm CMOS process, occupies 0.08 mm2, and consumes 1.5 mW of analog power at 2.5 V supply. The simulation results show that the dynamic range is 85.7 dB, while the out-of-band SNR is 40.5 dB.

A Wideband Continuous Time Quadrature Delta Sigma Modulator Based on a Real DSM for Low Power WLAN Receiver

2017 ◽  
Vol 27 (03) ◽  
pp. 1850044 ◽  
Author(s):  
Alireza Shamsi ◽  
Esmaeil Najafi Aghdam
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Continuous Time ◽  
Signal To Noise Ratio ◽  
System Level ◽  
Complex Coefficient ◽  
Loop Filter ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Excess Loop Delay

Power consumption and bandwidth are two of the most important parameters in design of low power wideband modulators as power consumption is growing with the increase in bandwidth. In this study, a multi bit wideband low-power continuous time feed forward quadrature delta sigma modulator (CT-FF-QDSM) is designed for WLAN receiver applications by eliminating adders from modulator structure. In this method, a real modulator is designed and its excess loop delay (ELD) is compensated, then, it is converted into a quadrature structure by applying the complex coefficient to loop filter. Complex coefficients are extracted by the aid of a genetic algorithm to further improve signal to noise ratio (SNR) for bandwidth. One of the disadvantages of CT-FF-QDSM is the adders of loop filters which are power hungry and reduce the effective loop gain. Therefore, the adders have been eliminated while the transfer function is intact in the final modulator. The system level SNR of the proposed modulator is 62.53[Formula: see text]dB using OSR of 12. The circuit is implemented in CMOSTSMC180nm technology. The circuit levels SNR and power consumption are 54[Formula: see text]dB and 13.5[Formula: see text]mW, respectively. Figure of Merit (FOM) obtained from the proposed modulator is about 0.824 (pj/conv) which is improved (by more than 40%) compared to the previous designs.

A 16-bit low-power double-sampled delta sigma modulator for audio applications

2015 ◽  
Author(s):  
Yongsheng Wang ◽  
Hongying Wang ◽  
Fengchang Lai ◽  
Bei Cao ◽  
Yang Liu ◽  
...  
Keyword(s):  
Low Power ◽  
Delta Sigma Modulator ◽  
Delta Sigma

scholarly journals A Low-Power Opamp-Less Second-Order Delta-Sigma Modulator for Bioelectrical Signals in 0.18 µm CMOS

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6456
Author(s):  
Fernando Cardes ◽  
Nikhita Baladari ◽  
Jihyun Lee ◽  
Andreas Hierlemann
Keyword(s):  
Low Power ◽  
Low Frequency ◽  
Cmos Technology ◽  
Low Noise ◽  
Second Order ◽  
Frequency Noise ◽  
Voltage Controlled Oscillator ◽  
Noise Shaping ◽  
Delta Sigma Modulator ◽  
Delta Sigma

This article reports on a compact and low-power CMOS readout circuit for bioelectrical signals based on a second-order delta-sigma modulator. The converter uses a voltage-controlled, oscillator-based quantizer, achieving second-order noise shaping with a single opamp-less integrator and minimal analog circuitry. A prototype has been implemented using 0.18 μm CMOS technology and includes two different variants of the same modulator topology. The main modulator has been optimized for low-noise, neural-action-potential detection in the 300 Hz–6 kHz band, with an input-referred noise of 5.0 μVrms, and occupies an area of 0.0045 mm2. An alternative configuration features a larger input stage to reduce low-frequency noise, achieving 8.7 μVrms in the 1 Hz–10 kHz band, and occupies an area of 0.006 mm2. The modulator is powered at 1.8 V with an estimated power consumption of 3.5 μW.

A Low Power and Small Area FFT Processor for OFDM Demodulator

2007 ◽  
Vol 53 (2) ◽  
pp. 274-277 ◽  
Author(s):  
Xiaojin Li ◽  
Zongsheng Lai ◽  
Jianmin Cui
Keyword(s):  
Low Power ◽  
Small Area ◽  
Fft Processor
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