Near-threshold adiabatic flip-flops based on PAL-2N circuits in nanometer CMOS processes

2010 ◽  
Author(s):  
Jianping Hu ◽  
Xiaoying Yu
Keyword(s):  
Nanometer Cmos ◽  
Near Threshold ◽  
Cmos Processes

Near-Threshold Flip-Flops Using Clocked Adiabatic Logic in Nanometer CMOS Processes

2011 ◽  
Vol 460-461 ◽  
pp. 837-842 ◽  
Author(s):  
Hai Yan Ni ◽  
Jian Ping Hu
Keyword(s):  
Single Phase ◽  
Energy Savings ◽  
Logic Circuits ◽  
Sequential Circuits ◽  
Clock Generator ◽  
Nanometer Cmos ◽  
Wide Range ◽  
Adiabatic Logic ◽  
Auxiliary Signal ◽  
Near Threshold

This paper presents adiabatic flip-flops operating on near-threshold supply voltages. The near-threshold adiabatic flip-flops and sequential circuits are realized with improved CAL (Clocked Adiabatic Logic) circuits using a single-phase power clock. An auxiliary clock generator is used to obtain the non-overlap sinusoidal auxiliary signal pair. A near-threshold mode-10 counter is implemented. All circuits are simulated using Predictive Technology Model (PTM) 45nm process. The near-threshold adiabatic circuits attain large energy savings over a wide range of frequencies, as compared with conventional static CMOS logic circuits.

P-Type ECRL Circuits for Gate-Leakage Reduction in Nanometer CMOS Processes with Gate Oxide Materials

2010 ◽  
Vol 29-32 ◽  
pp. 1919-1924 ◽  
Author(s):  
Wei Qiang Zhang ◽  
Yu Zhang ◽  
Jian Ping Hu
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Gate Oxide ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Power Supply Voltage ◽  
Flip Flop ◽  
Nanometer Cmos ◽  
P Type ◽  
Cmos Processes

With the decrease of the power supply voltage, the thickness of the gate oxide has been also scaled down in CMOS technologies using gate oxide materials. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. Base on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, this paper propose a P-type efficient charge recovery logic (P-ECRL) to reduce leakage dissipations in nanometer CMOS processes with gate oxide materials. For an example, a J-K flip-flop and a mode-10 counter using four-phase P-ECRL circuits are verified. All circuits are simulated using 90nm and 45nm CMOS processes with gate oxide materials. The proposed P-ECRL circuits show significant improvement in terms of power consumption over the traditional N-type ECRL counterparts.

Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration

2010 ◽  
Vol 39 ◽  
pp. 73-78 ◽  
Author(s):  
Jin Tao Jiang ◽  
Li Fang Ye ◽  
Jian Ping Hu
Keyword(s):  
Gate Oxide ◽  
Cmos Process ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Leakage Reduction ◽  
Nanometer Cmos ◽  
Benchmark Circuit ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Cmos Processes

Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.

P-Type Adiabatic Sequential Circuits for Leakage Reduction of Nanometer Circuits

2010 ◽  
Vol 159 ◽  
pp. 155-161
Author(s):  
Jin Tao Jiang ◽  
Yu Zhang ◽  
Jian Ping Hu
Keyword(s):  
Power Consumption ◽  
Leakage Power ◽  
Sequential Circuits ◽  
Technology Scaling ◽  
Nanometer Cmos ◽  
Gate Structure ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
P Type ◽  
Cmos Processes

With rapid technology scaling, the proportion of the leakage power catches up with dynamic power gradually. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. This paper presents adiabatic sequential circuits using P-type complementary pass-transistor adiabatic logic circuit (P-CPAL) to reduce the gate-leakage power dissipations. A practical sequential system with a mode-10 counter is demonstrated using the P-CPAL scheme. All circuits are simulated using HSPICE under 65nm and 90nm CMOS processes. Simulations show that the mode-10 counter using P-CPAL circuits obtains significant improvement in terms of power consumption over the traditional N-type CPAL counterparts.

A New P-Type Clocked Adiabatic Logic for Nanometer CMOS Processes with Gate Oxide Materials

2010 ◽  
Vol 29-32 ◽  
pp. 1930-1936 ◽  
Author(s):  
Jian Ping Hu ◽  
Li Fang Ye ◽  
Li Su
Keyword(s):  
Power Dissipation ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Total Power ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Nanometer Cmos ◽  
Adiabatic Logic ◽  
P Type ◽  
Cmos Processes

Leakage current is becoming a significant contributor to power dissipations in nanometer CMOS circuits due to the scaling of oxide thickness. This paper proposes a new P-type clocked adiabatic logic (P-CAL) to reduce gate leakage based on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones in nanometer CMOS processes using gate oxide materials. Based on the power dissipation models of adiabatic circuits, the estimation technology for the active leakage dissipations of P-CAL circuits is proposed. The active leakage dissipations are estimated by testing total leakage dissipations with additional load capacitances using SPICE simulations. Compared to N-type clocked adiabatic logic (N-CAL) circuits, the total power and leakage power dissipation of P-type CAL circuits are reduced greatly.

Leakage Reduction of Improved CAL Registers Using MTCMOS Power-Gating Scheme in Nanometer CMOS Processes

2010 ◽  
Vol 121-122 ◽  
pp. 281-286 ◽  
Author(s):  
Jia Guo Zhu ◽  
Jian Ping Hu
Keyword(s):  
Single Phase ◽  
Sleep Mode ◽  
Power Gating ◽  
Register File ◽  
Leakage Currents ◽  
Technology Scaling ◽  
Nanometer Cmos ◽  
Adiabatic Logic ◽  
X 32 ◽  
Cmos Processes

With rapid technology scaling, the leakage dissipation that begins to replace dynamitic dissipation is becoming a major source in CMOS circuits because of the increasing sub-threshold leakage current in nanometer CMOS processes. This paper introduces a MTCMOS power-gating technique, which is used for an adiabatic register file based on improved CAL (Clocked Adiabatic Logic) to reduce leakage dissipation in sleep mode. A 32 X 32 single-phase adiabatic register file are verified using HSPICE in different processes, threshold voltage, and active ratios, and BSIM4 model is adopted to reflect the leakage currents. Simulation results show that leakage losses are greatly reduced.

A Single-Phase Energy-Recovery Register Using Drowsy Cache and MTCMOS Techniques for Leakage Reductions

2010 ◽  
Vol 29-32 ◽  
pp. 1937-1942
Author(s):  
Hong Li ◽  
Jia Guo Zhu ◽  
Jian Ping Hu
Keyword(s):  
Leakage Current ◽  
Single Phase ◽  
Gate Oxide ◽  
Register File ◽  
Leakage Currents ◽  
Technology Scaling ◽  
Nanometer Cmos ◽  
Materials Simulation ◽  
X 32 ◽  
Cmos Processes

With rapid technology scaling, the leakage dissipation is becoming a major source in CMOS circuits because of the increasing sub-threshold and gate leakage current in nanometer CMOS processes. This paper presents an adiabatic register file based on improved CAL (Clocked Adiabatic Logic) using MTCMOS power-gating and drowsy cache techniques to reduce both sub-threshold leakage and gate oxide leakage current dissipations. A 32 X 32 single-phase adiabatic register file are verified using HSPICE. BSIM4 model is adopted to reflect leakage currents in nanometer CMOS processes with gate oxide materials. Simulation results show that leakage losses are greatly reduced.

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