Comments on "CMOS low-noise amplifier design optimization techniques"

2006 ◽  
Vol 54 (7) ◽  
pp. 3155 ◽  
Author(s):  
Jingxue Lu ◽  
Fengyi Huang
Keyword(s):  
Design Optimization ◽  
Low Noise ◽  
Optimization Techniques ◽  
Low Noise Amplifier ◽  
Amplifier Design ◽  
Noise Amplifier

CMOS Low-Noise Amplifier Design Optimization Techniques

2004 ◽  
Vol 52 (5) ◽  
pp. 1433-1442 ◽  
Author(s):  
T.-K. Nguyen ◽  
C.-H. Kim ◽  
G.-J. Ihm ◽  
M.-S. Yang ◽  
S.-G. Lee
Keyword(s):  
Design Optimization ◽  
Low Noise ◽  
Optimization Techniques ◽  
Low Noise Amplifier ◽  
Amplifier Design ◽  
Noise Amplifier

[Authors' reply to comments on "CMOS low-noise amplifier design optimization techniques"]

2006 ◽  
Vol 54 (7) ◽  
pp. 3155-3156 ◽  
Author(s):  
Trung-Kien Nguyen ◽  
Chung-Hwam Kim ◽  
Gook-Ju Ihm ◽  
Moon-Su Yang ◽  
Sang-Gug Lee
Keyword(s):  
Design Optimization ◽  
Low Noise ◽  
Optimization Techniques ◽  
Low Noise Amplifier ◽  
Amplifier Design ◽  
Noise Amplifier

Image-rejection CMOS low-noise amplifier design optimization techniques

2005 ◽  
Vol 53 (2) ◽  
pp. 538-547 ◽  
Author(s):  
Trung-Kien Nguyen ◽  
Nam-Jin Oh ◽  
Choong-Yul Cha ◽  
Yong-Hun Oh ◽  
Gook-Ju Ihm ◽  
...  
Keyword(s):  
Design Optimization ◽  
Low Noise ◽  
Optimization Techniques ◽  
Low Noise Amplifier ◽  
Image Rejection ◽  
Amplifier Design ◽  
Noise Amplifier

scholarly journals A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application

2017 ◽  
Vol 7 (1.3) ◽  
pp. 69
Author(s):  
M. Ramana Reddy ◽  
N.S Murthy Sharma ◽  
P. Chandra Sekhar
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Low Power Consumption ◽  
Common Gate ◽  
Chip Size ◽  
Overall Performance ◽  
Amplifier Design ◽  
Noise Amplifier

The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.

scholarly journals CMOS Ultra-Wideband Low Noise Amplifier Design

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
K. Yousef ◽  
H. Jia ◽  
R. Pokharel ◽  
A. Allam ◽  
M. Ragab ◽  
...  
Keyword(s):  
Impedance Matching ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Output Impedance ◽  
Integrated Inductor ◽  
Technology Process ◽  
Amplifier Design ◽  
Noise Amplifier

This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB LNA whose bandwidth extends from 2.5 GHz to 16 GHz is designed using a symmetric 3D RF integrated inductor. This UWB LNA has a gain of 11 ± 1.0 dB and a NF less than 3.3 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8 V supply. The UWB LNA is designed and simulated in standard TSMC 0.18 µm CMOS technology process.

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