Compact modeling of intrinsic capacitances in Double-Gate Tunnel-FETs

2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) ◽

10.1109/ulis.2017.7962584 ◽

2017 ◽

Author(s):

A. Farokhnejad ◽

M. Graef ◽

F. Horst ◽

C. Liu ◽

Q.T. Zhao ◽

...

Keyword(s):

Compact Modeling ◽

Double Gate ◽

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Influence of Localized Interface Charges on Drain Current of Dual-Material Double-Gate Tunnel FETs

2018 3rd International Conference for Convergence in Technology (I2CT) ◽

10.1109/i2ct.2018.8529418 ◽

2018 ◽

Author(s):

Sanjay Kumar ◽

Kamlaksha Baral ◽

Sweta Chander ◽

P. K. Singh ◽

Kunal Singh ◽

...

Keyword(s):

Drain Current ◽

Double Gate ◽

Interface Charges ◽

Tunnel Fets ◽

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Compact modeling of quantum effects in symmetric double-gate MOSFETs

Microelectronics Journal ◽

10.1016/j.mejo.2010.05.007 ◽

2010 ◽

Vol 41 (10) ◽

pp. 688-692 ◽

Author(s):

Wei Wang ◽

Huaxin Lu ◽

Jooyoung Song ◽

Shih-Hsien Lo ◽

Yuan Taur

Keyword(s):

Quantum Effects ◽

Compact Modeling ◽

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Performance of asymmetric gate oxide on gate-drain overlap in Si and Si1−xGex double gate tunnel FETs

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2016.7593036 ◽

2016 ◽

Author(s):

S. Poorvasha ◽

B. Lakshmi

Keyword(s):

Double Gate ◽

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Compact modeling of subthreshold swing in double gate and nanowire MOSFETs, for Si and GaAs channel materials

Solid-State Electronics ◽

10.1016/j.sse.2015.06.008 ◽

2015 ◽

Vol 111 ◽

pp. 188-195 ◽

Author(s):

G. Hiblot ◽

Q. Rafhay ◽

F. Boeuf ◽

G. Ghibaudo

Keyword(s):

Subthreshold Swing ◽

Compact Modeling ◽

Double Gate ◽

Nanowire Mosfets

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Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach

Planar Double-Gate Transistor ◽

10.1007/978-1-4020-9341-8_3 ◽

2009 ◽

pp. 27-54

Author(s):

Daniela Munteanu ◽

Jean-Luc Autran

Keyword(s):

Compact Modeling ◽

Double Gate ◽

Physical Approach ◽

Double Gate Mosfet

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Dual-Metal Graded-Channel Double-Gate Tunnel FETs for Reduction of Ambipolar Conduction

2018 IEEE Electron Devices Kolkata Conference (EDKCON) ◽

10.1109/edkcon.2018.8770449 ◽

2018 ◽

Author(s):

Chandan K. Pandey ◽

Saurabh Chaudhury

Keyword(s):

Double Gate ◽

Tunnel Fets ◽

Ambipolar Conduction

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Analytical compact modeling framework for the 2D electrostatics in lightly doped double-gate MOSFETs

Solid-State Electronics ◽

10.1016/j.sse.2011.11.023 ◽

2012 ◽

Vol 69 ◽

pp. 72-84 ◽

Author(s):

Mike Schwarz ◽

Thomas Holtij ◽

Alexander Kloes ◽

Benjamín Iñíguez

Keyword(s):

Compact Modeling ◽

Double Gate ◽

Modeling Framework

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Double-gate Ge, In As-based tunnel FETs with enhanced ON-current

2016 International Conference on Communication and Signal Processing (ICCSP) ◽

10.1109/iccsp.2016.7754219 ◽

2016 ◽

Author(s):

Chebrolu Gopi ◽

Sudakar Singh Chauhan

Keyword(s):

Double Gate ◽

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Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs

Japanese Journal of Applied Physics ◽

10.7567/1347-4065/ab6569 ◽

2020 ◽

Vol 59 (SG) ◽

pp. SGGA06

Author(s):

Koichi Fukuda ◽

Naoya Nogami ◽

Shogo Kunisada ◽

Yasuyuki Miyamoto

Keyword(s):

Double Gate ◽

Device Design ◽

Design Scheme ◽

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Investigation of geometrical and doping parameter variations on GaSb/Si‐based double gate tunnel FETs: A qualitative and quantitative approach for RF performance enhancement

International Journal of Numerical Modelling Electronic Networks Devices and Fields ◽

10.1002/jnm.2633 ◽

2019 ◽

Vol 32 (6) ◽

Author(s):

Poorvasha Shanmuganathan ◽

Lakshmi Balasubramanian

Keyword(s):

Performance Enhancement ◽

Quantitative Approach ◽

Double Gate ◽

Qualitative And Quantitative ◽

Parameter Variations ◽

Tunnel Fets ◽

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