A variable-latency, ultra-low-voltage RISC processor with a new in-situ error detection and correction technique
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2015 ◽
Vol 50
(6)
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pp. 1478-1490
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Keyword(s):
2019 ◽
Vol 27
(8)
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pp. 1886-1896
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2011 ◽
Vol 60
(10)
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pp. 1511-1516
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1990 ◽
Vol 137
(1)
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pp. 88
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2014 ◽
Vol 61
(12)
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pp. 952-956
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