Effect of Warpage of Flip Chip Packages Due to the Underfill Encapsulating Process on Interconnect Reliability

2009 ◽  
Vol 131 (3) ◽  
Author(s):  
Satoru Katsurayama ◽  
Hironori Tohmyoh
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Capillary Flow ◽  
Curing Process ◽  
Assembly Process ◽  
Test Circuit ◽  
Interconnect Reliability ◽  
Flip Chip Packaging ◽  
Underfill Material

In flip chip packages, it is common practice for interconnects to be encapsulated with a liquid underfill material. This paper describes the effects of different underfill processes, i.e., the conventional capillary-flow underfill and two no-flow underfill processes, on flip chip packaging. The warpage of the package was examined, and the value of this during three different underfill encapsulating processes was measured. In addition, the interconnect reliability of the bump bonds after thermal-cycling was evaluated using a test circuit. The warpage of the package before curing varied depending on the assembly process, but that after curing was almost the same for all the processes studied. It was found that the interconnect reliability is closely related to the differences in the warpage arising from the assembly process, and that the smaller change in warpage introduced by the curing process gave a higher interconnect reliability for the bump bonds. Based on these findings, lower curing temperatures are considered to be more effective for improving the mountability of the package and the interconnect reliability.

The Study of Underfill Epoxy Hardness in Reducing Curing Process Time for Flip Chip Packaging

2011 ◽  
Vol 462-463 ◽  
pp. 1194-1199
Author(s):  
Zainudin Kornain ◽  
Azman Jalar ◽  
Rozaidi Rashid ◽  
Shahrum Abdullah
Keyword(s):  
Thermal Expansion ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Process Time ◽  
Curing Process ◽  
Curing Time ◽  
Hold Temperature ◽  
Flip Chip Packaging ◽  
Time Cycle ◽  
The Impact

Underfilling is the vital process to reduce the impact of the thermal stress that results from the mismatch in the co-efficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. This paper reported the pattern of underfill’s hardness during curing process for large die Ceramic Flip Chip Ball Grid Array (FC-CBGA). A commercial amine based underfill epoxy was dispensed into HiCTE FC-CBGA and cured in curing oven under a new method of two-step curing profile. Nano-identation test was employed to investigate the hardness of underfill epoxy during curing steps. The result has shown the almost similar hardness of fillet area and centre of the package after cured which presented uniformity of curing states. The total curing time/cycle in production was potentially reduced due to no significant different of hardness after 60 min and 120 min during the period of second hold temperature.

Surface Energy and Wettability Study of Flip Chip Packaging Materials

2011 ◽  
Vol 2011 (1) ◽  
pp. 000961-000970
Author(s):  
Jinlin Wang
Keyword(s):  
Surface Energy ◽  
Flip Chip ◽  
Substrate Surface ◽  
Solid Surfaces ◽  
Energy Calculation ◽  
Assembly Process ◽  
Flip Chip Packaging ◽  
Materials Used ◽  
Lead Free Solders ◽  
Ic Package

The surface energy of solid surfaces and surface tension of liquids are important parameters in the IC package assembly process. Wettability analyses have been completed for various materials used in the assembly process of flip chip packages, including underfills, substrates, fluxes, and lead free solders. We will highlight some of these results in this paper. We will focus our discussion on substrate surface energy analysis. A brief discussion of different surface energy methods and the liquid selection criteria will be given. The advantage and limitation of the surface energy calculation methods will be discussed. The data from several case studies will be presented. Our results show that contact angle and surface energy measurements are very useful for quality control and product development where interfacial properties are important.

An Optimization of Two-Steps Curing Profile to Eliminate Voids Formation in Underfill Epoxy for Hi-CTE Flip Chip Packaging

2010 ◽  
Vol 97-101 ◽  
pp. 23-27 ◽  
Author(s):  
Zainudin Kornain ◽  
Azman Jalar ◽  
Rozaidi Rashid ◽  
Shahrum Abdullah
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Ball Grid Array ◽  
Statistic Analysis ◽  
Curing Process ◽  
Ceramic Ball ◽  
Die Attach ◽  
Ball Grid Array Package ◽  
Flip Chip Packaging ◽  
The Impact

Underfilling is the preferred process to reduce the impact of the thermal stress that results from the mismatch in the coefficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. Voids formation in underfill is considered as failure in flip chip manufacturing process. Voids formation possibly caused by several factors such as poor soldering and flux residue during die attach process, voids entrapment due moisture contamination, dispense pattern process and setting up the curing process. This paper presents the optimization of two steps curing profile in order to reduce voids formation in underfill for Hi-CTE Flip Chip Ceramic Ball Grid Array Package (FC-CBGA). A C-Mode Scanning Aqoustic Microscopy (C-SAM) was used to scan the total count of voids after curing process. Statistic analysis was conducted to analyze the suitable curing profile in order to minimize or eliminate the voids formation. It was shown that the two steps curing profile provided solution for void elimination.

High Yield, Near Void-Free Assembly Process of a Flip Chip in Package Using No-Flow Underfill

2010 ◽  
Vol 2010 (1) ◽  
pp. 000798-000805 ◽  
Author(s):  
Sangil Lee ◽  
Daniel F. Baldwin
Keyword(s):  
Flip Chip ◽  
Void Nucleation ◽  
Void Formation ◽  
Bubble Nucleation ◽  
Nucleation Theory ◽  
High Yield ◽  
Process Conditions ◽  
Assembly Process ◽  
Fine Pitch ◽  
Underfill Material

The advanced assembly process for a flip chip in package (FCIP) using no-flow underfill material presents challenges with high I/O density (over 3000 I/O) and fine-pitch (down to 150 μm) interconnect applications because it has narrowed the feasible assembly process window for achieving robust interconnect yield. In spite of such challenges, a high yield, nearly void-free assembly process has been achieved in the past research using commercial no-flow underfill material with a high I/O, fine pitch FCIP. The initial void area (approximately 7% ) could cause early failures such solders fatigue cracking or solder bridging in thermal reliability. Therefore, this study reviewed a classical bubble nucleation theory to predict the conditions of underfill void nucleation in the no flow assembly process. Based on the models prediction, systematic experiments were designed to eliminate underfill voiding using parametric studies. First, a void formation study investigated the effect of reflow parameter on underfill voiding and found process conditions of void-free assembly with robust interconnections. Second, a void formation characterization validated the determined reflow conditions to achieve a high yield and void-free assembly process, and the stability of assembly process using a large scale of assemblies respectively. This paper presents systematic studies into void formation study and void formation characterization through the use of structured experimentation which was designed to achieve a high yield, void-free assembly process leveraging a void formation model based on classical bubble nucleation theory. Indeed, the theoretical models were in good agreement with experimental results.

Underflow Process for Direct-Chip-Attachment Packaging

1998 ◽  
Vol 515 ◽  
Author(s):  
P. C. Li ◽  
G. L. Lehmann ◽  
J. Cascio ◽  
T. Driscoll ◽  
Y. J. Huang ◽  
...  
Keyword(s):  
Flip Chip ◽  
Capillary Flow ◽  
Flow Behavior ◽  
Complex Function ◽  
Plane Channel ◽  
Flow Process ◽  
Wetting Properties ◽  
Solder Bumps ◽  
Flip Chip Packaging ◽  
Measured Flow

ABSTRACTIn flip-chip packaging an underfill mixture is placed into the chip-to-substrate standoff created by the array of solder bumps, using a capillary flow process. The flow behavior is a complex function of the mixture properties, the wetting properties, and the flow geometry. This paper reports on the use of a plane channel capillary flow to characterize underfill materials. The measured flow behavior provides evidence that both the contact angle (θ) and the suspension viscosity (μapp) vary with time under the Influence of changing flow conditions. This nonlinear fluid behavior is modeled for the flow of both model suspensions and commercial underfill materials using an extended Washburn model.

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