A Hybrid Antenna in Package Solution Using FOWLP Technology

2021 ◽  
Author(s):  
XueSong Zhang ◽  
Qian Wang ◽  
Bo Wang ◽  
Gang Wang ◽  
Xin Gu ◽  
...  
Keyword(s):  
Millimeter Wave ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Transmission Loss ◽  
Rapid Development ◽  
Coplanar Waveguide ◽  
Organic Substrate ◽  
Hybrid Integration ◽  
Wafer Level ◽  
Monolithic Integrated Circuit

Abstract Widespread millimeter wave applications have promoted rapid development of System in Package (SiP) and Antenna in Package (AiP). Most AiP structures take the form of flip chip on antenna substrate, where interconnect losses are caused by solder bumps, and manufacturing difficulties may be encountered for chips with fine pad pitches. Fan-out wafer level package (FOWLP) with antenna patterning on Redistributed Layers (RDL) is another method for mm-wave AiP realization. In this project a hybrid integration AiP structure is developed. The Microwave Monolithic Integrated Circuit (MMIC) chip and antenna unit are integrated with chip-first FOWLP process. By using multilayer organic substrate and fine pitch RDL interconnection, proper antenna performance and lower transmission loss can be achieved. Modified coplanar waveguide is adopted to feed 2x2 aperture array formed on RDL. Package warpage is evaluated using ANSYS and Shadow Moire measurement. The antenna realizes bandwidth 25% and gain 8.5dBi using aperture-coupled stacked patch for 60GHz digital communication system. The proposed approach is a convenient solution for the hybrid integration of millimeter wave AiP systems.

scholarly journals Metamaterial CRLH Antennas on Silicon Substrate for Millimeter-Wave Integrated Circuits

2012 ◽  
Vol 2012 ◽  
pp. 1-9 ◽  
Author(s):  
Gheorghe Ioan Sajin ◽  
Iulia Andreea Mocanu
Keyword(s):  
Integrated Circuits ◽  
Millimeter Wave ◽  
Integrated Circuit ◽  
Silicon Substrate ◽  
Return Loss ◽  
Coplanar Waveguide ◽  
Radiation Characteristic ◽  
Millimetric Wave ◽  
Monolithic Integrated Circuit ◽  
Left Handed

The paper presents two composite right/left-handed (CRLH) coplanar waveguide (CPW) zeroth-order resonant (ZOR) antennas which were designed, processed, and electrically characterized for applications in the millimetric wave frequency range. Two CRLH antennas were developed forf=27 GHz andf=38.5, GHz, respectively. The CRLH antenna onf=27 GHz shows a return loss ofRL<−18.78 dB atf=26.88 GHz. The −3 dB radiation characteristic beamwidth was approximately 37° and the gain wasGi=2.82 dBi. The CRLH antenna onf=38.5 GHz has a return loss ofRL<−38.5 dB atf=38.82 GHz and the −3 dB radiation characteristic beamwidth of approximately 17°. The gains wereGi=1.08 dBi atf=38 GHz andGi=1.2 dBi atf=38.6 GHz. The maximum measured gain wasGi=1.75 dBi atf=38.2 GHz. It is, upon the authors' knowledge, the first report of millimeter wave CRLH antennas on silicon substrate in CPW technique for use in mm-wave monolithic integrated circuit.

scholarly journals A RF Redundant TSV Interconnection for High Resistance Si Interposer

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 169
Author(s):  
Mengcheng Wang ◽  
Shenglin Ma ◽  
Yufeng Jin ◽  
Wei Wang ◽  
Jing Chen ◽  
...  
Keyword(s):  
Millimeter Wave ◽  
High Frequency ◽  
High Performance ◽  
Rapid Development ◽  
Coplanar Waveguide ◽  
Equivalent Circuit Model ◽  
High Resistivity ◽  
Performance Requirements ◽  
Wave Radar ◽  
Interconnect Design

Through Silicon Via (TSV) technology is capable meeting effective, compact, high density, high integration, and high-performance requirements. In high-frequency applications, with the rapid development of 5G and millimeter-wave radar, the TSV interposer will become a competitive choice for radio frequency system-in-package (RF SIP) substrates. This paper presents a redundant TSV interconnect design for high resistivity Si interposers for millimeter-wave applications. To verify its feasibility, a set of test structures capable of working at millimeter waves are designed, which are composed of three pieces of CPW (coplanar waveguide) lines connected by single TSV, dual redundant TSV, and quad redundant TSV interconnects. First, HFSS software is used for modeling and simulation, then, a modified equivalent circuit model is established to analysis the effect of the redundant TSVs on the high-frequency transmission performance to solidify the HFSS based simulation. At the same time, a failure simulation was carried out and results prove that redundant TSV can still work normally at 44 GHz frequency when failure occurs. Using the developed TSV process, the sample is then fabricated and tested. Using L-2L de-embedding method to extract S-parameters of the TSV interconnection. The insertion loss of dual and quad redundant TSVs are 0.19 dB and 0.46 dB at 40 GHz, respectively.

Inkjet and 3D Printing Technology for Fundamental Millimeter-Wave Wireless Packaging

2018 ◽  
Vol 15 (3) ◽  
pp. 101-106
Author(s):  
Bijan K. Tehrani ◽  
Ryan A. Bahr ◽  
Manos M. Tentzeris
Keyword(s):  
3D Printing ◽  
Millimeter Wave ◽  
Integrated Circuit ◽  
Coplanar Waveguide ◽  
Frequency Selective Surface ◽  
60 Ghz ◽  
Low Loss ◽  
Printing Technology ◽  
3D Printing Technology ◽  
Application Specific

Abstract This article outlines the design, processing, and implementation of inkjet and 3D printing technologies for the development of fully printed, highly integrated millimeter-wave (mm-wave) wireless packages. The materials, tools, and processes of each technology are outlined and justified for their respective purposes. Inkjet-printed 3D interconnects directly interfacing a packaging substrate with an integrated circuit (IC) die are presented using printed dielectric ramps and coplanar waveguide transmission lines exhibiting low loss (.6–.8 dB/mm at 40 GHz). Stereolithography 3D printing is presented for the encapsulation of IC dice, enabling the application-specific integration of on-package structures, including dielectric lenses and frequency selective surface–based wireless filters. Finally, inkjet and 3D printing technology are combined to present sloped mm-wave interconnects through an encapsulant, or through mold vias, achieving a slope of up to 65° and low loss (.5–.6 dB/mm at 60 GHz). The combination of these additive techniques is highlighted for the development of scalable, application-specific wireless packages.

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

2007 ◽  
Vol 129 (4) ◽  
pp. 460-468 ◽  
Author(s):  
Karan Kacker ◽  
Thomas Sokol ◽  
Wansuk Yun ◽  
Madhavan Swaminathan ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Dielectric Material ◽  
Coefficient Of Thermal Expansion ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Integrative Approach ◽  
Wafer Level ◽  
Target Values ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

Design and fabrication of MEMS-type compliant overhang flip-chip interconnect for RF applications

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 002082-002094
Author(s):  
Pingye Xu ◽  
Michael C. Hamilton
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Organic Substrate ◽  
Process Temperature ◽  
High Yield ◽  
Wafer Level ◽  
Micro Fabrication ◽  
Compliant Interconnect ◽  
Sac Solder

With the increase of I/O density and scaling of interconnects, conventional solder ball interconnects are required to be made smaller. As a result, the reliability of the conventional solder ball flip-chip interconnects worsens. One method to mitigate this issue is by using underfill. However, underfill undermines the reworkability of the solder joints and is challenging to apply when the gap between chip and substrate is small. Another approach to enhance the reliability is to use taller solder ball interconnects, which is however usually more costly. Instead of using conventional solder ball interconnects, compliant interconnects have also been researched in the past few decades to mitigate the reliability issue. The use of compliant structures can compensate for the coefficient of thermal expansion (CTE) mismatch between a Si chip and an organic substrate. In this work, we present the design and fabrication of MEMS-type compliant overhang flip-chip interconnects. The structures are placed at the end of a coplanar waveguide (CPW) as interconnects between CPWs to research their performance at radio frequency (RF). A micro-fabrication process was adopted to build the interconnects. The CPWs are fabricated using conventional e-beam deposition followed by photolithography and then copper electroplating. The compliant overhangs were fabricated on top of a dome of reflowed photoresist on the CPWs to form a curved shape. The reflow and hard bake of the photoresist requires a process temperature of above 220 °C, which is similar to the reflow temperature of a Sn-Ag-Cu (SAC) solder. Therefore we believe our process is compatible with SAC solder processing infrastructures in terms of process temperature. The fabricated structures show high yield and uniformity. Due to the use of a micro-fabrication based process, the structures have the potential to be scaled and be compatible to wafer level packaging. The CPWs were then flip-chip bonded with the compliant interconnect as transitions. The RF performance of the interconnects up to 50 GHz will be presented.

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