Polymeric aperture masks for high performance organic integrated circuits

2004 ◽  
Vol 22 (4) ◽  
pp. 1892-1895 ◽  
Author(s):  
Dawn V. Muyres ◽  
Paul F. Baude ◽  
Steven Theiss ◽  
Michael Haase ◽  
Tommie W. Kelley ◽  
...  
Author(s):  
C.K. Wu ◽  
P. Chang ◽  
N. Godinho

Recently, the use of refractory metal silicides as low resistivity, high temperature and high oxidation resistance gate materials in large scale integrated circuits (LSI) has become an important approach in advanced MOS process development (1). This research is a systematic study on the structure and properties of molybdenum silicide thin film and its applicability to high performance LSI fabrication.


IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 813-826
Author(s):  
Farid Uddin Ahmed ◽  
Zarin Tasnim Sandhie ◽  
Liaquat Ali ◽  
Masud H. Chowdhury

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1304
Author(s):  
Raquel Fernández de Cabo ◽  
David González-Andrade ◽  
Pavel Cheben ◽  
Aitor V. Velasco

Efficient power splitting is a fundamental functionality in silicon photonic integrated circuits, but state-of-the-art power-division architectures are hampered by limited operational bandwidth, high sensitivity to fabrication errors or large footprints. In particular, traditional Y-junction power splitters suffer from fundamental mode losses due to limited fabrication resolution near the junction tip. In order to circumvent this limitation, we propose a new type of high-performance Y-junction power splitter that incorporates subwavelength metamaterials. Full three-dimensional simulations show a fundamental mode excess loss below 0.1 dB in an ultra-broad bandwidth of 300 nm (1400–1700 nm) when optimized for a fabrication resolution of 50 nm, and under 0.3 dB in a 350 nm extended bandwidth (1350–1700 nm) for a 100 nm resolution. Moreover, analysis of fabrication tolerances shows robust operation for the fundamental mode to etching errors up to ± 20 nm. A proof-of-concept device provides an initial validation of its operation principle, showing experimental excess losses lower than 0.2 dB in a 195 nm bandwidth for the best-case resolution scenario (i.e., 50 nm).


2019 ◽  
Vol 12 (1) ◽  
Author(s):  
Zhuang Hui ◽  
Ming Xiao ◽  
Daozhi Shen ◽  
Jiayun Feng ◽  
Peng Peng ◽  
...  

Abstract With the increase in the use of electronic devices in many different environments, a need has arisen for an easily implemented method for the rapid, sensitive detection of liquids in the vicinity of electronic components. In this work, a high-performance power generator that combines carbon nanoparticles and TiO2 nanowires has been fabricated by sequential electrophoretic deposition (EPD). The open-circuit voltage and short-circuit current of a single generator are found to exceed 0.7 V and 100 μA when 6 μL of water was applied. The generator is also found to have a stable and reproducible response to other liquids. An output voltage of 0.3 V was obtained after 244, 876, 931, and 184 μs, on exposure of the generator to 6 μL of water, ethanol, acetone, and methanol, respectively. The fast response time and high sensitivity to liquids show that the device has great potential for the detection of small quantities of liquid. In addition, the simple easily implemented sequential EPD method ensures the high mechanical strength of the device. This compact, reliable device provides a new method for the sensitive, rapid detection of extraneous liquids before they can impact the performance of electronic circuits, particularly those on printed circuit board.


Author(s):  
Ms. Mayuri Ingole

Utilization of power is a major aspect in the design of integrated circuits. Since, adders are mostly employed in these circuits, we should design them effectively. Here, we propose an easy and effective method in decreasing the maximum consumption of power. Carry Select Adder is the one which is dependent on the design of two adders. We present a high performance low-power adder that is implemented. Also, here in Carry Select Adder, Binary Excess Code-1is replaced by Ripple Carry Adder. After analyzing the results, we can come to a conclusion that the architecture which is proposed will have better results in terms of consumption of power compared to conventional techniques. 


2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.


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