A Low-Power Edge Detection Technique for Sensor Wake-Up Applications

2015 ◽  
Vol 24 (10) ◽  
pp. 1550157 ◽  
Author(s):  
Yao Wang ◽  
Haibo Wang ◽  
Guangjun Wen
Keyword(s):  
Edge Detection ◽  
Low Power ◽  
Process Variations ◽  
Design Guidelines ◽  
Detection Sensitivity ◽  
Ultra Low Power ◽  
Mos Transistor ◽  
Detection Circuit ◽  
Current Change ◽  
Small Voltage

A novel low-power edge detection circuit is presented in this work. Upon the arrival of signal falling edge, the proposed design establishes a small voltage difference between the gate and source terminals of a MOS transistor which slightly increases the MOS transistor leakage current. A current integration-based approach is used to robustly sense the current change and subsequently detect the signal falling edge. The design is suitable for ultra-low-power sensor wake-up circuits. Design guidelines for achieving optimal detection sensitivity as well as the implementation of calibration circuits for coping with process variations and mismatches are discussed in the paper. Simulation results are presented to demonstrate the performance of the proposed circuit.

scholarly journals Circuit and System Design Guidelines for Ultra-low Power Sensor Nodes

2013 ◽  
Vol 6 (0) ◽  
pp. 17-26 ◽  
Author(s):  
Yoonmyung Lee ◽  
Dongmin Yoon ◽  
Yejoong Kim ◽  
David Blaauw ◽  
Dennis Sylvester
Keyword(s):  
Low Power ◽  
System Design ◽  
Design Guidelines ◽  
Sensor Nodes ◽  
Ultra Low Power ◽  
Circuit And System ◽  
Power Sensor

An ultra low-power low-voltage programmable temperature detection circuit

2011 ◽  
Author(s):  
Alfredo Olmos ◽  
Stefano Pietri ◽  
Ricardo Coimbra ◽  
Murillo Franco Neto ◽  
Jefferson D. B. Soldera
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Ultra Low Power ◽  
Temperature Detection ◽  
Detection Circuit

Design guidelines for ultra-low power gateways in environment monitoring wireless sensor networks

2017 ◽  
Author(s):  
Maximus Byamukama ◽  
Janet Nakato Nannono ◽  
Kabonire Ruhinda ◽  
Bjorn Pehrson ◽  
Mary Nsabagwa ◽  
...  
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Low Power ◽  
Design Guidelines ◽  
Wireless Sensor ◽  
Environment Monitoring ◽  
Ultra Low Power

scholarly journals Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8302
Author(s):  
Cancio Monteiro ◽  
Yasuhiro Takahashi
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Complexity ◽  
Process Variations ◽  
Cmos Technology ◽  
Process Technology ◽  
Two Phase ◽  
Ultra Low Power ◽  
Ambient Temperatures

Low-power and secure crypto-devices are in crucial demand for the current emerging technology of the Internet of Things (IoT). In nanometer CMOS technology, the static and dynamic power consumptions are in a very critical challenge. Therefore, the FinFETs is an alternative technology due to its superior attributes of non-leakage power, intra-die variability, low-voltage operation, and lower retention voltage of SRAMs. In this study, our previous work on CMOS two-phase clocking adiabatic physical unclonable function (TPCA-PUF) is evaluated in a FinFET device with a 4-bits PUF circuit complexity. The TPCA-PUF-based shorted-gate (SG) and independent-gate (IG) modes of FinFETs are investigated under various ambient temperatures, process variations, and ±20% of supply voltage variations. To validate the proposed TPCA-PUF circuit, the QUALPFU-based Fin-FETs are compared in terms of cyclical energy dissipation, the security metrics of the uniqueness, the reliability, and the bit-error-rate (BER). The proposed TPCA-PUF is simulated using 45 nm process technology with a supply voltage of 1 V. The uniqueness, reliability, and the BER of the proposed TPCA-PUF are 50.13%, 99.57%, and 0.43%, respectively. In addition, it requires a start-up power of 18.32 nW and consumes energy of 2.3 fJ/bit/cycle at the reference temperature of 27 °C.

Challenges and Limitations of Low Power Techniques

2016 ◽  
pp. 48-70
Author(s):  
Vandana B. ◽  
Patro B. S.
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Semiconductor Device ◽  
Low Voltage ◽  
Supply Voltage ◽  
Oxide Semiconductor ◽  
Gate Length ◽  
Ultra Low Power ◽  
Mos Transistor ◽  
Contemporary World

In contemporary world the technology has kept its vast identity in developing ultra NANO devices to give up the compact device utilities, in VLSI, Metal Oxide Semiconductor device plays an key role in power dissipation product, in terms of MOS theory characteristics it is predefined that a MOS transistor can conduct easily with low voltage which gives low power but in DSM technology there is a likelihood to achieve ultra low power, so this can be achieved due to the rapid shrinking of gate length, here the chapter deals with challenges and limitations of low power techniques. The predominant way to generate low power is to start with the fundamental principles that are defined in the existing technologies that it gives low power with less leakage current. Apart from this parameter consideration is also required to achieve this. The successful and the major parameter in generating low power is that the shrinking of supply voltage. To go through this, upcoming sections gives the brief idea about the different techniques that are utilized to generate low power with less leakage.

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