A Low-Power Mixed-Mode SIMO Universal Gm–C Filter

2017 ◽  
Vol 26 (10) ◽  
pp. 1750164 ◽  
Author(s):  
Mostafa Parvizi ◽  
Abouzar Taghizadeh ◽  
Hamid Mahmoodian ◽  
Ziaadin Daei Kozehkanani

This paper describes a new single-input multiple-output (SIMO) mixed-mode universal biquad [Formula: see text]–[Formula: see text] filter. It can realize all kinds of filter responses including high-pass, band-pass, low-pass, band-stop and all-pass filters, simultaneously. Moreover, in this structure, all of these filters in all states of voltage mode, current mode, transresistance mode and transconductance mode are achieved by the same topology without any convertor. The proposed filter employs three operational transconductance amplifiers (OTAs) with four inputs and one output, three fully differential OTAs and two grounded capacitors. In other words, this filter is composed of six [Formula: see text] blocks and two grounded capacitors. The grounded capacitors are suitable for integrated circuit implementation. In order to reduce the power consumption, the OTAs are biased in subthreshold region. In addition, sensitivity analysis is included to show the low active and passive sensitivity performances of the filter. This filter is designed and simulated in HSPICE with 0.18[Formula: see text][Formula: see text]m model CMOS technology parameters. The simulation results show that the filter consumes only 75[Formula: see text][Formula: see text]W and operates at 1.5[Formula: see text]MHz with [Formula: see text]0.5[Formula: see text]V supply voltages and capacitors [Formula: see text][Formula: see text]pF.

2013 ◽  
Vol 787 ◽  
pp. 501-507
Author(s):  
Saksit Summart ◽  
Chanchai Thongsopa

This article presents current-mode universal biquad filters based on CDTAs. The filter circuits using four CDTAs and two grounded capacitors which are able to provide low-pass, high-pass, band-pass, band-reject and all-pass functions. The pole frequency can be orthogonally controlled from quality factor and the circuits have high output impedance appropriate for cascade connection application in current mode which is capable to directly drive load. This qualification is very appropriate for further development into an integrated circuit. The results of PSPICE simulation program are corresponding to the theoretical analysis.


2019 ◽  
Vol 29 (10) ◽  
pp. 2050162 ◽  
Author(s):  
Data R. Bhaskar ◽  
Ajishek Raj ◽  
Pragati Kumar

This paper introduces an electronically tunable mixed-mode universal biquad filter configuration employing four single output operational transconductance amplifiers (OTAs), one dual output OTA and two grounded capacitors (GCs) (ideal for integrated circuit implementation and absorbing shunt parasitic capacitances). The presented structure can realize all second-order filter functions, namely, low pass (LP), high pass (HP), band pass (BP), band reject (BR) and all pass (AP) responses in voltage mode (VM), current mode (CM), transresistance mode (TRM) and transconductance mode (TCM) using appropriate selection(s) of input signals. The cut-off frequency ([Formula: see text] and bandwidth (BW) of the realized filters can be tuned orthogonally through the transconductance (by varying the bias currents) of the OTAs. The proposed biquad configuration enjoys low active and passive sensitivities. The workability of this multifunctional biquad filter topology has been confirmed through simulations using MATLAB and Analog Design Environment (ADE) spectre tool provided by Cadence Virtuoso, using 0.18[Formula: see text][Formula: see text]m CMOS process parameter. The post-layout simulations have also been carried out to validate the theory.


2018 ◽  
Vol 27 (12) ◽  
pp. 1850196 ◽  
Author(s):  
Bhartendu Chaturvedi ◽  
Jitendra Mohan ◽  
Atul Kumar

The paper introduces a new versatile universal biquadratic configuration based on two fully differential second generation current conveyors without need of input matching conditions. The proposed circuit consists of two fully differential second generation current conveyors, four resistors and two grounded capacitors. The proposed biquad configuration provides all five standard filtering responses: low-pass, high-pass, band-pass, band-reject and all-pass in voltage-mode, transadmittance-mode, current-mode and transimpedance-mode. The proposed circuit is single-input multiple-outputs type, so all responses are available simultaneously. Moreover, extra inverting amplifier and double-type amplifier are also not required in the proposed circuit for any filtering response. The nonideal and parasitic effects of fully differential second generation current conveyor on the proposed circuit have also been investigated. HSPICE simulation results have been incorporated to validate the proposal.


2007 ◽  
Vol 16 (04) ◽  
pp. 507-516 ◽  
Author(s):  
SHAHRAM MINAEI ◽  
ERKAN YUCE

In this paper, a universal current-mode second-order active-C filter for simultaneously realizing low-pass, band-pass and high-pass responses is proposed. The presented filter employs only three plus-type second-generation current-controlled conveyors (CCCII+s). This filter needs no critical active and passive component matching conditions and no additional active and passive elements for realizing high output impedance low-pass, band-pass and high-pass characteristics. The angular resonance frequency (ω0) and quality factor (Q) of the proposed resistorless filter can be tuned electronically. To verify the theoretical analysis and to exhibit the performance of the proposed filter, it is simulated with SPICE program.


2009 ◽  
Vol 18 (07) ◽  
pp. 1287-1308 ◽  
Author(s):  
EMAN A. SOLIMAN ◽  
SOLIMAN A. MAHMOUD

This paper presents different novel CMOS realizations for the differential difference operational floating amplifier (DDOFA). The DDOFA was first introduced in Ref. 1 and was used to realize different analog circuits like integrators, filters and variable gain amplifiers. New CMOS realizations for the DDOFA are introduced in this literature. Furthermore the DDOFA is modified to realize a fully differential current conveyor (FDCC). Novel CMOS realizations of the FDCC are presented. The FDCC is used to realize second-order band pass–low-pass filter. Performance comparisons between the different realizations of the DDOFA and FDCC are given in this literature. PSPICE simulations of the overall proposed circuits are given using 0.25 μm CMOS Technology from TMSC MOSIS model and dual supply voltages of ±1.5 V.


2017 ◽  
Vol 24 (1) ◽  
pp. 79-89
Author(s):  
Bogdan Pankiewicz

Abstract In this paper a programmable input mode instrumentation amplifier (IA) utilising second generation, multiple output current conveyors and transmission gates is presented. Its main advantage is the ability to choose a voltage or current mode of inputs by setting the voltage of two configuration nodes. The presented IA is prepared as an integrated circuit block to be used alone or as a sub-block in a microcontroller or in a field programmable gate array (FPGA), which shall condition analogue signals to be next converted by an analogue-to-digital converter (ADC). IA is designed in AMS 0.35 µm CMOS technology and the power supply is 3.3 V; the power consumption is approximately 9.1 mW. A linear input range in the voltage mode reaches ± 1.68 V or ± 250 µA in current mode. A passband of the IA is above 11 MHz. The amplifier works in class A, so its current supply is almost constant and does not cause noise disturbing nearby working precision analogue circuits.


2016 ◽  
Vol 25 (12) ◽  
pp. 1650154 ◽  
Author(s):  
Ahmet Abaci ◽  
Erkan Yuce

In this paper, two new second-order voltage-mode universal filters are proposed. Both of the proposed filters use only two differential voltage current conveyors (DVCCs), four resistors and two grounded capacitors which are advantageous from integrated circuit technology point of view. They can simultaneously provide second-order low-pass, high-pass, band-pass, notch and all-pass responses. They offer orthogonal control of angular resonance frequency and quality factor. However, they have a single matching condition for only all-pass responses. A number of simulations based on SPICE program are accomplished in order to demonstrate the performance of both filters.


2013 ◽  
Vol 22 (01) ◽  
pp. 1250064 ◽  
Author(s):  
NEETA PANDEY ◽  
SAJAL K. PAUL

The configuration with electronic tunable characteristics that can work in mixed mode may be useful from IC realization viewpoint and application adaptability. This paper proposes an electronically tunable mixed mode universal filter based on multiple output current controlled current conveyor (MOCCCII) and this single topology without any alteration can be used in all four modes i.e., voltage (VM), current (CM), transimpedance (TIM) and transadmittance (TAM). The architecture uses four MOCCCIIs and two grounded capacitors; and can realize universal filter functions — low pass (LP), band pass (BP), high pass (HP), notch (NF) and all pass (AP) for all four modes. Moreover the input impedance is high and output impedance is low for voltage signal and vice-versa for current signal, hence the proposed topology is suitable for cascading for all four modes. The workability of the proposed circuit has been verified via SPICE simulations using AMS 0.35 μm CMOS technology.


2021 ◽  
Author(s):  
Tao Wang

Point-to-point parallel links are widly used in short-distance high-speed data communications. For these links, the design goal is not only to integrate a large number of I/Os in the systems, but also to increase the bit rate per I/O. The cost per I/O has to be kept low as performance improves. Voltage and timing error sources limit the performance of data links and affect its robustnest. These kinds of noise impose greater challenges in parallel data links, such as inter-signal timing skew and inter-signal cross-talk. The use of low-cost schemes, such as single-ended signaling, is effected signaficantly [sic] by the voltage and timging [sic] noise. Fully differential signaling schemes, two physical paths per signal channel, significantly increases the cost of system. Therefore, overcoming the voltage noise, keeping the cost low are two challenges in high-speed parallel links. In this thesis, we propose a new current-mode signaling scheme current-mode incremtnal [sic] signaling for high-speed parallel links. Also, the circuits of the receiver called current-integrating receiver are presented. To assess the effectiveness of the proposed signaling scheme, a 4-bit parallel link consisting of four bipolar current-mode drivers, five 10 cm microstrip lines with a FR4 substrate, and four proposed current-integrating receivers is implemented in UMC 0.13[micro]m, 1.2V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the proposed current-mode incremental signaling scheme and the current-integrating receiver are capable of transmitting parallel data at 2.5 Gbyte/s.


Electronics ◽  
2019 ◽  
Vol 8 (7) ◽  
pp. 765 ◽  
Author(s):  
Leila Safari ◽  
Gianluca Barile ◽  
Giuseppe Ferri ◽  
Vincenzo Stornelli

In this paper, a new low-voltage low-power dual-mode universal filter is presented. The proposed circuit is implemented using inverting current buffer (I-CB) and second-generation voltage conveyors (VCIIs) as active building blocks and five resistors and three capacitors as passive elements. The circuit is in single-input multiple-output (SIMO) structure and can produce second-order high-pass (HP), band-pass (BP), low-pass (LP), all-pass (AP), and band-stop (BS) transfer functions. The outputs are available as voltage signals at low impedance Z ports of the VCII. The HP, BP, AP, and BS outputs are also produced in the form of current signals at high impedance X ports of the VCIIs. In addition, the AP and BS outputs are also available in inverting type. The proposed circuit enjoys a dual-mode operation and, based on the application, the input signal can be either current or voltage. It is worth mentioning that the proposed filter does not require any component matching constraint and all sensitivities are low, moreover it can be easily cascadable. The simulation results using 0.18 μm CMOS technology parameters at a supply voltage of ±0.9 V are provided to support the presented theory.


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