A Linear VCO Using Single CFA and Analog Multipliers: Quadrature Oscillator Implementation

2021 ◽  
Author(s):  
K. Mathur ◽  
P. Venkateswaran ◽  
R. Nandi
Keyword(s):  
Noise Figure ◽  
Short Circuit ◽  
Open Loop ◽  
Control Voltage ◽  
Voltage Controlled Oscillator ◽  
Quadrature Oscillator ◽  
Loop Transfer Function ◽  
Band Pass ◽  
Linearity Error ◽  
Linear Voltage

A new linear voltage-controlled oscillator (LVCO) implementation using single AD-844 CFA with a pair of AD-835 multiplier devices and a pair of grounded capacitors is proposed. The open-loop transfer function of the topology is analyzed wherein the concept of Short-Circuit Natural Frequency (SCNF) is applied to derive the sinusoid oscillator implementation. The proposed oscillator circuit is then restructured to yield a linear voltage-controlled quadrature oscillator (LVCQO) after appropriate cascade with a CFA-based active integrator. The oscillation frequency is linearly tunable ([Formula: see text][Formula: see text]MHz) by the multiplier control voltage ([Formula: see text]. Subsequently, a high-[Formula: see text] selective band-pass (BP) filter is derived. Effects of the CFA port roll-off parameters and its parasitic capacitors ([Formula: see text] had been analyzed to be negligible. Measured oscillator response exhibited a THD [Formula: see text]%, a linearity error ([Formula: see text]% and a phase noise figure of ([Formula: see text]104 dBc/Hz at 24-kHz offset.

scholarly journals CMOS RF Front-Ends For Bluetooth Applications

2021 ◽  
Author(s):  
Yanmei Li
Keyword(s):  
Flicker Noise ◽  
Noise Figure ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Low Noise ◽  
Control Voltage ◽  
Voltage Controlled Oscillator ◽  
Power Added Efficiency ◽  
Common Gate ◽  
Offset Frequency

This project investigates the design of RF front-ends for bluetooth applications. The main objectives in each design are optimized noise figure, power consumption, gain and linearity. The designed cascode LNA achieves 1.37 dB low noise figure through ports matching and maximizes the voltage gain to 11.5 dB. The port isolation reaches to 82 dB. A 2 MHz low IF down-conversion mixer is developed. It employs current injection to reduce the flicker noise of MOSFETs. The total noise figure of the mixer is 17 dB and input referred IIP3 is 4.97 dB. A quadrature mixer constructed by two symmetric Gilbert mixers are discussed. A common-gate class E power amplifier is investigated. Through connecting a L matching network, the output power would be 17.7 dBm at 1.4 V power supply and the power added efficiency PAE and drain efficiency DE are 41% and 42.8 % respectively. To supply two LO frequencies with 90º phase difference, a quadrature voltage controlled oscillator is designed using a series of coupling structure and accumulation mode PMOS varactors. The frequency tuning range is 2.304 GHz ~ 2.54 GHz when the control voltage changes from 0 to 0.7 V. The QVCO exhibits phase noise of -113 dBc/Hz at 600 kHz offset frequency and -119 dBc.Hz at 1 MHz offset frequency. All the circuits were designed in TSMC-0.18μm 1.8 V CMOS technology and simulated using HSPICE RF simulator.

scholarly journals CMOS RF Front-Ends For Bluetooth Applications

2021 ◽  
Author(s):  
Yanmei Li
Keyword(s):  
Flicker Noise ◽  
Noise Figure ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Low Noise ◽  
Control Voltage ◽  
Voltage Controlled Oscillator ◽  
Power Added Efficiency ◽  
Common Gate ◽  
Offset Frequency

This project investigates the design of RF front-ends for bluetooth applications. The main objectives in each design are optimized noise figure, power consumption, gain and linearity. The designed cascode LNA achieves 1.37 dB low noise figure through ports matching and maximizes the voltage gain to 11.5 dB. The port isolation reaches to 82 dB. A 2 MHz low IF down-conversion mixer is developed. It employs current injection to reduce the flicker noise of MOSFETs. The total noise figure of the mixer is 17 dB and input referred IIP3 is 4.97 dB. A quadrature mixer constructed by two symmetric Gilbert mixers are discussed. A common-gate class E power amplifier is investigated. Through connecting a L matching network, the output power would be 17.7 dBm at 1.4 V power supply and the power added efficiency PAE and drain efficiency DE are 41% and 42.8 % respectively. To supply two LO frequencies with 90º phase difference, a quadrature voltage controlled oscillator is designed using a series of coupling structure and accumulation mode PMOS varactors. The frequency tuning range is 2.304 GHz ~ 2.54 GHz when the control voltage changes from 0 to 0.7 V. The QVCO exhibits phase noise of -113 dBc/Hz at 600 kHz offset frequency and -119 dBc.Hz at 1 MHz offset frequency. All the circuits were designed in TSMC-0.18μm 1.8 V CMOS technology and simulated using HSPICE RF simulator.

scholarly journals A 2-bit, 3.1 GS/s, band-pass DSM receiver for active antenna systems

2013 ◽  
Vol 5 (3) ◽  
pp. 329-334 ◽  
Author(s):  
Udo Karthaus ◽  
Stephan Ahles ◽  
Ahmed Elmaghraby ◽  
Horst Wagner
Keyword(s):  
Integrated Circuit ◽  
Dynamic Range ◽  
Noise Figure ◽  
Base Stations ◽  
Active Antenna ◽  
Single Carrier ◽  
Bicmos Technology ◽  
Band Pass ◽  
Time Band ◽  
Antenna Systems

This paper presents a radio frequency (RF) continuous-time band-pass delta sigma modulator (CT BP DSM) receiver realized in a 180 nm SiGe BiCMOS technology. It also provides an introduction to active antenna systems (AAS) for cellular infrastructure base stations, which is the target application for this RF integrated circuit (IC). The internal quantizer and feedback digital to analog converter (DAC) resolution of the CT BP DSM is 2 bit. Without applying DAC linearization techniques such as trimming or dynamic element matching being utilized, measured performance parameters include an SNR and SNDR in 35 MHz bandwidth of 56.7 and 53.7 dB, respectively. IIP3 and noise figure are −6.6 dBm and 10 dB, respectively. No image reception is noticeable within a measurement dynamic range of 83 dB. When driven by single-carrier and three-carrier W-CDMA signals, adjacent channel leakage ratio (ACLR) is −62.6 and −52.1 dB, respectively, making the design also suitable as a modulator for a class-S power amplifier.

scholarly journals Theory and Design of a Flexible Two-Stage Wideband Wilkinson Power Divider

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2168
Author(s):  
Antra Saxena ◽  
Mohammad Hashmi ◽  
Deepayan Banerjee ◽  
Muhammad Akmal Chaudhary
Keyword(s):  
Transfer Function ◽  
Transmission Lines ◽  
Short Circuit ◽  
Wide Band ◽  
Power Divider ◽  
Design Parameters ◽  
Two Stage ◽  
Quarter Wave ◽  
Band Pass ◽  
Wilkinson Power Divider

This article presents the design scheme of a wideband Wilkinson Power Divider (WPD) with two-stage architecture utilizing quarter-wave transmission lines and short-circuit stubs. The bandwidth of the proposed WPD is flexible and can be controlled using the design parameters. The proposed design achieves excellent isolation between output ports in addition good in-band performance. The analysis of the proposed circuit results in a simplified transfer function which is then equated with a standard band-pass transfer function to determine the parameters of transmission lines, stub’s impedances, and the value of the isolation resistors. Furthermore, it is also demonstrated that a simple alteration in the proposed circuit enables the design of a wideband DC isolated WPD that maintains a good in-band and isolation performance. A number of case studies have been included to highlight the flexibility of the proposed design. Two distinct prototypes are developed on different boards to demonstrate the wideband performance of the proposed design. An excellent agreement between the experimental and measured results for both the designs over a wide band including very good isolation between ports validate the proposed design.

A Scalable Millimetre-Wave Differential CMOS Cross-Coupled VCO for Automotive Radar Application

2018 ◽  
Vol 27 (10) ◽  
pp. 1850158 ◽  
Author(s):  
Rekha Yadav ◽  
Pawan Kumar Dahiya ◽  
Rajesh Mishra
Keyword(s):  
Phase Noise ◽  
Oxide Semiconductor ◽  
Control Voltage ◽  
Cmos Process ◽  
Operating Voltage ◽  
Voltage Controlled Oscillator ◽  
Automotive Radar ◽  
Millimetre Wave ◽  
The Impact ◽  
Lc Vco

In this paper, a novel method to realize LC Voltage-Controlled-Oscillator (LC-VCO) operating at 76.2–76.7[Formula: see text]GHz frequency band for microwave RFIC component is presented. The model of cross-coupled differential LC-VCO is designed in 45[Formula: see text]nm technology using Complementary Metal Oxide Semiconductor (CMOS) process for Frequency Modulated Carrier Wave (FMCW) automotive radar sensors and RF transceivers application. The impact of VDD, control voltage and temperature variation on frequency shift, phase noise, and output power has been analyzed to optimize the trade-off between frequency, phase noise, and power requirement. The results depict that LC-VCO dissipates 10.45[Formula: see text]mW power at an operating voltage of 1.5[Formula: see text]V. The phase noise has been observed to be [Formula: see text]90[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset at 76[Formula: see text]GHz carrier frequency. The estimated layout area of IC is [Formula: see text]m2. The result shows the edge of the design over existing techniques.

Miniaturized Bandpass Filter with Wide Stopband using Spiral Configuration of Stepped Impedance Resonator

Frequenz ◽  
2018 ◽  
Vol 72 (9-10) ◽  
pp. 455-458 ◽  
Author(s):  
Vivek Singh ◽  
Vinay Kumar Killamsetty ◽  
Biswajeet Mukherjee
Keyword(s):  
Bandpass Filter ◽  
Short Circuit ◽  
Band Pass Filter ◽  
Pass Filter ◽  
Transmission Zeros ◽  
Quarter Wavelength ◽  
Rejection Level ◽  
Compact Size ◽  
Band Pass ◽  
Stepped Impedance Resonator

Abstract In this letter, a miniaturized Band Pass Filter (BPF) with wide stopband centered at 0.350 GHz for TETRA band applications is proposed using a Spiral Short Circuit quarter wavelength Stepped Impedance Resonator (SSC-SIR) and a stub loaded on feed line for enhancement of rejection level in the stopband. Spiral configuration of the resonator is used for the miniaturization of BPF. The proposed BPF provides a 3dB fractional bandwidth of 13.7 % with two transmission zeros in the lower and upper stopband to provide good selectivity and four transmission zeros which provide wide stopband upto 6.86f0. Proposed BPF has a very compact size of 0.064λg×0.062λg.

Analisa Elemen Multiarms Resonator Open Loop Pada Band-Pass Filter Mikrostrip Yang Bekerja Di Frekuensi EHF

2021 ◽  
Vol 8 (2) ◽  
pp. 93-104
Author(s):  
M. Reza Hidayat ◽  
Difa Dwi Juliantara Sukmawan
Keyword(s):  
Bandpass Filter ◽  
Open Loop ◽  
Band Pass Filter ◽  
Pass Filter ◽  
A Value ◽  
Resonator Design ◽  
Band Pass ◽  
Patch Width ◽  
Simulation Results ◽  
Patch Length

The use of bandpass filters is commonly used but the use of specifications varies depending on needs, in this case the microstrip bandpass filter is expected to observe the multiarms characteristics of the open loop resonator on the performance of the bandpass filter for EHF frequencies. The design of this microstrip bandpass filter uses a multiarms open loop resonator design where at the beginning of the simulation stage uses only 1 arm with patch width, arm spacing, feeder line width and patch length based on trial and error. The final simulation results are obtained with a connector distance of 2 mm and a distance of 1 mm between arms with a value of S11 = -13.8 dB and S21 = -2.8 dB at a frequency of 30.8 GHz based on the simulation results. The filter has been successfully fabricated but cannot be measured because the frequency is too high and the measuring instrument cannot measure the frequency

scholarly journals Modeling and Stability Analysis of Parallel Inverters in Island Microgrid

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 463 ◽  
Author(s):  
Xiaohuan Wang ◽  
Hongyang Qing ◽  
Peng Huang ◽  
Chunjiang Zhang
Keyword(s):  
Parallel System ◽  
Open Loop ◽  
Power Equipment ◽  
Control Methods ◽  
Impedance Model ◽  
Loop Transfer Function ◽  
Impedance Modeling ◽  
The Difference ◽  
Output Characteristics ◽  
The Stability

The island microgrid is composed of a large number of inverters and various types of power equipment, and the interaction between inverters with different control methods may cause system instability, which will cause the power equipment to malfunction. Therefore, effective methods for analyzing the stability of the microgrid system have become particularly important. Generally, impedance modeling methods are used to analyze the stability of power electronic converter systems. In this paper, the impedance models of a PQ-controlled inverter and droop-controlled inverter are established in d-q frame. In view of the difference of output characteristics between the two control methods, the island microgrid is equivalent to a double closed-loop system. The impedance model of the parallel system is derived and the open loop transfer function of the system is extracted. Based on the generalized Nyquist criterion (GNC), the stability of parallel system working in island microgrid mode is analyzed using this proposed impedance model. The simulation and experiment results are presented to verify the analysis.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Dead Zone ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Control Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Cmos Inverter ◽  
Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

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