An Interpolated Flying-Adder-Based Frequency Synthesizer

This work presents an interpolated flying-adder- (FA-) based frequency synthesizer. The architecture of an interpolated FA, which uses an interpolated multiplexer (MUX) to replace the multiplexer in conventional flying adder, improves the cycle-to-cycle jitter and root-mean-square (RMS) jitter performance. A multiphase all-digital phase-locked loop (ADPLL) provides steady reference signals for the interpolated flying adder. This paper reveals implementation skills of a multiphase ADPLL, as well as an interpolated flying adder. In addition, analytical details of the jitter performance are derived. A test chip for the proposed interpolated FA-based frequency synthesizer was fabricated in a standard 0.18 μm CMOS technology, and the core area was 0.143 mm2. The output frequency had a range of 33 MHz ~ 286 MHz at 1.8 V with peak-to-peak (Pk-Pk) jitter 215.2 ps at 286 MHz/1.8 V.

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An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS

International Journal of Microwave Science and Technology ◽

10.1155/2013/584341 ◽

2013 ◽

Vol 2013 ◽

pp. 1-11 ◽

Cited By ~ 3

Author(s):

Sang-yeop Lee ◽

Hiroyuki Ito ◽

Shuhei Amakawa ◽

Noboru Ishihara ◽

Kazuya Masu

Keyword(s):

Phase Noise ◽

High Frequency ◽

Reference Signal ◽

Phase Locked Loop ◽

Cmos Technology ◽

Injection Locking ◽

The Other ◽

Pulse Injection ◽

Noise Characteristics ◽

Reference Signals

An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL area: 0.11 mm2) by adopting 90 nm Si CMOS technology. The proposed circuit is configured with two cascaded PLLs; one of them is a reference PLL that generates reference signals to the other one from low-frequency external reference signals. The other is a main PLL that generates high-frequency output signals. A high-frequency half-integral subharmonic locking technique was used to decrease the phase noise characteristics. For a 50 MHz input reference signal, without injection locking, the 1 MHz offset phase noise was −88 dBc/Hz at a PLL output frequency of 7.2 GHz (= 144 × 50 MHz); with injection locking, the noise was −101 dBc/Hz (spur level: −31 dBc; power consumption from a 1.0 V power supply: 25 mW).

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Experimental Value of Percent Variation in Root-Mean-Square Ex-Core Detector Signal to the Core Barrel Amplitude Scale Factor

Nuclear Technology ◽

10.13182/nt80-a32459 ◽

1980 ◽

Vol 48 (2) ◽

pp. 122-127 ◽

Cited By ~ 3

Author(s):

J. P. Thompson ◽

G. R. McCoy ◽

B. T. Lubin

Keyword(s):

Root Mean Square ◽

Scale Factor ◽

Mean Square ◽

The Core ◽

Detector Signal

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A Low Jitter Dual Output Frequency Synthesizer Using Phase-Locked Loop for Smart Audio Devices

Journal of the Institute of Electronics and Information Engineers ◽

10.5573/ieie.2016.53.2.027 ◽

2016 ◽

Vol 53 (2) ◽

pp. 27-35

Author(s):

Ye-Seul Baek ◽

Jeong-Yun Lee ◽

Hyuk Ryu ◽

Jongyeon Lee ◽

Donghyun Baek

Keyword(s):

Frequency Synthesizer ◽

Phase Locked Loop ◽

Output Frequency ◽

Low Jitter

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A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and −251.6 dB FoM

Sensors ◽

10.3390/s21227648 ◽

2021 ◽

Vol 21 (22) ◽

pp. 7648

Author(s):

Shi Zuo ◽

Jianzhong Zhao ◽

Yumei Zhou

Keyword(s):

Phase Noise ◽

Root Mean Square ◽

Supply Voltage ◽

Cmos Process ◽

Type I ◽

Voltage Controlled Oscillator ◽

Mean Square ◽

Frequency Range ◽

Output Frequency ◽

Zero Phase

This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and −251.6 dB FoM.

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Design of All Digital Phase Locked Loop for Wireless Applications

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i3.12.16513 ◽

2018 ◽

Vol 7 (3.12) ◽

pp. 836

Author(s):

Swetha R ◽

J Manjula ◽

A Ruhan bevi

Keyword(s):

Frequency Synthesizer ◽

Phase Locked Loop ◽

Cmos Technology ◽

Phase Detector ◽

Ring Oscillator ◽

Frequency Range ◽

Loop Filter ◽

Wireless Applications ◽

Digital Phase ◽

Operating Frequency Range

This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW.

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A Low Power CMOS Temperature Sensor

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.284-287.1729 ◽

2013 ◽

Vol 284-287 ◽

pp. 1729-1733

Author(s):

Shu Chung Yi

Keyword(s):

Power Consumption ◽

Low Power ◽

Temperature Sensor ◽

Supply Voltage ◽

Temperature Monitoring ◽

Ring Oscillator ◽

Core Area ◽

Output Frequency ◽

The Core ◽

Low Power Cmos

This Paper Proposed a Low-power Smart Temperature Sensor. the Sensor Consisted of a PTAT Circuit, and a Ring Oscillator. the Current of the PTAT Circuit Was Used to Drive the Ring Oscillator which Generates a Temperature Related Signal. the Sensor Was Implemented by the TSMC CMOS 0.35 µm 2P4M Digital Process. the Core Aµµrea Is only 1105.59 µm2. the Power Consumption Is aboutµ 159.15 nw. the Linearity between the Output Frequency and Temperature Is Marked by R-square Rule. the Value of the Linearity Is 0.991 during the Temperature Range. the Proposed Sensor Required only One Supply Voltage. the Core Area Was Small. Therefore, the Sensor Was Suitable for Embedded in any Circuit that Required Temperature Monitoring.

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