scholarly journals Performance analysis of ultrathin junctionless double gate vertical MOSFETs

2019 ◽  
Vol 8 (4) ◽  
Author(s):  
K. E. Kaharudin ◽  
Z. A. F. M. Napiah ◽  
F. Salehuddin ◽  
A. S. M. Zain ◽  
Ameer F. Roslan
Keyword(s):  
Performance Analysis ◽  
Process Simulation ◽  
Doping Concentration ◽  
Drain Current ◽  
Double Gate ◽  
Subthreshold Slope ◽  
Main Challenge ◽  
Channel Engineering ◽  
The Impact ◽  
Vertical Mosfets

The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability.

scholarly journals Analysis of analog and RF behaviors in junctionless double gate vertical MOSFET

2020 ◽  
Vol 9 (1) ◽  
pp. 101-108
Author(s):  
K. E. Kaharudin ◽  
Z. A. F. M. Napiah ◽  
F. Salehuddin ◽  
A. S. M. Zain ◽  
Ameer F. Roslan
Keyword(s):  
Concentration Gradient ◽  
Process Simulation ◽  
Doping Concentration ◽  
Double Gate ◽  
Device Structure ◽  
Junction Device ◽  
Junctionless Transistor ◽  
Channel Engineering ◽  
The Impact ◽  
Better Than

The prime obstacle in continuing the transistor’s scaling is to maintain ultra-shallow source/drain (S/D) junctions with high doping concentration gradient, which definitely demands an advanced and complicated S/D and channel engineering. Junctionless transistor configuration has been found to be an alternative device structure in which the junction and doping gradients could be totally eliminated, thus simplifying the fabrication process. In this paper, a process simulation has been performed to study the impact of junctionless configuration on the analog and RF behaviors of double-gate vertical MOSFET. The result proves that the performance of n-channel junctionless double-gate vertical MOSFET (n-JLDGVM) is slightly better than the junction double-gate vertical MOSFET (n-JDGVM). Junctionless device exhibits better analog behaviors as the transconductance (gm) is increased by approximately 4%. In term of RF behaviors, the junctionless device exhibits 3.4% and 7% higher cut-off frequency (fT) and gain band-width product (GBW) respectively over the junction device.

Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

2021 ◽  
Author(s):  
SHIKHA U S ◽  
Rekha K James ◽  
Jobymol Jacob ◽  
Anju Pradeep
Keyword(s):  
Drain Current ◽  
Gate Oxide ◽  
Negative Capacitance ◽  
Double Gate ◽  
High K ◽  
Gate Control ◽  
Effect Transistor ◽  
Dimensional Simulation ◽  
The Impact ◽  
Low K

Abstract The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (Av), which is an important parameter in NC devices is also analyzed.

Modeling and Simulation of Nanoscale Lateral Gaussian Doped Channel Asymmetric Double Gate MOSFET

2015 ◽  
Vol 36 ◽  
pp. 51-63 ◽  
Author(s):  
Vandana Kumari ◽  
Manoj Saxena ◽  
Mridula Gupta
Keyword(s):  
Analytical Modeling ◽  
Current Model ◽  
Drain Current ◽  
Doping Profile ◽  
Mode Analysis ◽  
Double Gate ◽  
Digital Performance ◽  
Dg Mosfet ◽  
Double Gate Mosfet ◽  
The Impact

This work presents the drain current model using Evanescent Mode Analysis (EMA) for nanoscale Double Gate MOSFET having Gaussian doping profile along the horizontal direction in the channel i.e. from source to drain region. Due to heavily doped channel, band gap narrowing effect is incorporated in the analytical modeling scheme. The various parameters evaluated in this work using analytical modeling scheme are surface potential, electric field, threshold voltage, sub-threshold slope and drain current. The impact of peak Gaussian doping profile on the drain current and trans-conductance has been demonstrated which are important for assessing the analog performance of the device. The results are also compared with the uniformly doped DG MOSFET. The asymmetric behaviour of Gaussian doped DG MOSFET has also been investigated. In addition to this, digital performance of Gaussian doped DG MOSFET has also been assessed using exhaustive device simulation.

scholarly journals Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

2019 ◽  
Vol 9 (4) ◽  
pp. 2863
Author(s):  
K. E. Kaharudin ◽  
F. Salehuddin ◽  
A. S. M. Zain ◽  
Ameer F. Roslan
Keyword(s):  
Process Design ◽  
Concentration Level ◽  
Drain Current ◽  
Channel Length ◽  
Electrical Performance ◽  
Double Gate ◽  
Electrical Characteristics ◽  
Metal Gate ◽  
The Impact ◽  
Gate Work Function

The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.

Potential of 4H-SiC CMOS for High Temperature Applications Using Advanced Lateral p-MOSFETs

2016 ◽  
Vol 858 ◽  
pp. 821-824 ◽  
Author(s):  
Matthaeus Albrecht ◽  
Tobias Erlbacher ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
Threshold Voltage ◽  
Doping Concentration ◽  
Drain Current ◽  
Transfer Characteristic ◽  
Propagation Delay ◽  
Channel Mobility ◽  
Propagation Delay Time ◽  
Respective Field ◽  
Channel Lengths ◽  
The Impact

In this work, the impact of the n-well doping concentration on the channel mobility and threshold voltage of p-MOSFETs and their applications in CMOS-devices is evaluated. For this purpose lateral p-channel MOSFETs with different channel lengths (L = 800 μm, 10 μm, 5 μm, and 3 μm) and doping concentrations (ND = 1015 cm-3 and 8·1015 cm-3) were fabricated and the respective field-effect mobility was extracted from the transfer-characteristics. Comparable to n-MOSFETs the mobility of p-MOSFETs was found to be the highest for the lowest doping concentration in the channel and the absolute value of the threshold voltage increases with increasing doping concentration [4]. To investigate its suitability for CMOS applications, inverters with different doping concentrations for n-MOSFET (NA = 1015 cm-3 and 1017 cm-3) und p-MOSFET (ND = 1015 cm-3 and 8·1015 cm-3) were built. For logic levels of 0 V and 10 V, the voltage transfer characteristic with the highest input ranges was obtained for a low p-MOSFET and a high n-MOSFET doping concentration. The lowest propagation delay time could be achieved with a low p-MOSFET and a low n-MOSFET doping concentration. At room temperature as well as at high temperatures T = 573 K the drain current of p-MOSFETs with channel lengths below 3 μm is hampered by the series resistance of the source and drain region which limits the performance of CMOS devices.

THE IMPACT OF CHANNEL ENGINEERING ON SHORT CHANNEL BEHAVIOR OF NANO FIN-FETs

2012 ◽  
Vol 11 (02) ◽  
pp. 1250021
Author(s):  
RITI KUMARI ◽  
MANISH GOSWAMI ◽  
B. R. SINGH
Keyword(s):  
Concentration Profile ◽  
Doping Concentration ◽  
Short Note ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Engineering ◽  
Channel Effects ◽  
Uniform Channel ◽  
The Impact ◽  
Optimum Doping Concentration

This short note presents the simulation result on the effect of channel engineering i.e., non-uniform channel doping on short channel effects (SCE) in nano Fin-FET devices using Silvaco TCAD tool. The nano Fin-FET structures were generated using DEVEDIT and the effect of channel doping concentration has been studied. The optimum doping concentration profile has been observed to considerably improve the SCE in general and drain induced barrier lowering (DIBL) in particular.

scholarly journals Performance Analysis of User Pairing Algorithm in Full-Duplex Cellular Networks

2017 ◽  
Vol 2017 ◽  
pp. 1-12 ◽  
Author(s):  
Wonjong Noh ◽  
Wonjae Shin ◽  
Hyun-Ho Choi
Keyword(s):  
Performance Analysis ◽  
Low Complexity ◽  
Base Station ◽  
Cellular System ◽  
Throughput Maximization ◽  
Full Duplex ◽  
Radio Resource ◽  
User Pairing ◽  
Main Challenge ◽  
The Impact

In a full duplexing (FD) wireless cellular network, a base station operates in FD mode, while the downlink (DL) and uplink (UL) users operate in half duplexing (HD) mode. Thus, the downlink and uplink transmissions occur simultaneously so that interuser interference from a UL to a DL user occurs. In an FD network, the main challenge to minimize the interuser interference is user pairing, which determines a pair of DL and UL users who use the same radio resource simultaneously. We formulate a nonconvex optimization problem for user pairing to maximize the cell throughput. Then, we propose a heuristic user pairing algorithm with low complexity. This algorithm is designed such that the DL user having a better signal quality has higher priority to choose its paired UL user for throughput maximization. Thereafter, we conduct theoretical performance analysis of the FD cellular system based on stochastic geometry and analyze the impact of the user paring algorithm on the performance of the FD cellular system. Results show that the FD system that uses the proposed user pairing algorithm effectively reduces the interuser interference and approaches optimal performance. It also considerably outperforms the FD system using a random user pairing and almost doubles the conventional HD system in terms of cell throughput.

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