scholarly journals Approximate arithmetic circuits

2020 ◽  
Vol 9 (3) ◽  
pp. 183
Author(s):  
Navabharath Reddy G ◽  
Sruti Setlam ◽  
V. Prakasam ◽  
D. Kiran Kumar
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Integrated Circuit Design ◽  
Compressor Design ◽  
Low Power Dissipation ◽  
Human Sense ◽  
Error Distance

Low power consumption is the necessity for the integrated circuit design in CMOS technology of nanometerscale. Recent research proves that to achieve low power dissipation, implementation of approximate designs is the best design when compared to accurate designs. In most of the multimedia ap- plications, DSP blocks has been used as the core blocks. Most of the video and image processing algorithms implemented by these DSP blocks, where result will be in the form of image or video for human observing. As human sense of observation isless, the output of the DSP blocks allows being numerically approx- imate instead of being accurate. The concession on numerical exactness allows proposing approximate analysis. In this project approximate adders, approximate compressors and multipliers are proposed. Two approximate adders namely PA1 and PA2 are proposed which are of type TGA which provides better results like PA1 comprises of 14 transistors and 2 error distance, achieves reduction in delay by 64.9 % and reduction in power by 74.33% whereas the TGA1 had 16 transistors and more power dissipation.PA2 comprises of 20 transistors and 2 error distance. Similarly PA2 achieves delay reduction by 51.43%, power gets reduced by 67.2%. PDP is reduced by 61.97 % whereas TGA2 had 22 transistors. Approximate 4-2 compressor was proposed in this project to reduce number of partial produt. The compressor design in circuit level took 30 transistors with 4 errors out of 16 combinations whereas existing compressor design 1took 38 and design 2 took 36 transistors. By using the proposed adder and compressors, approximate 4x4 multiplier is proposed. The proposed multiplier achieves delay 124.56 (ns) and power 29.332 (uW)which is reduced by 68.01% in terms of delay and 95.97 % in terms of power when compared to accurate multiplier.

AN ADIABATIC 4:2 COMPRESSOR DESIGN FOR LOW POWER VLSI

1999 ◽  
Vol 09 (05n06) ◽  
pp. 339-346 ◽  
Author(s):  
K. W. NG ◽  
K. T. LAU
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Integrated Circuit Design ◽  
Power Efficient ◽  
Adiabatic Switching ◽  
Power Integrated Circuit ◽  
Adiabatic Logic ◽  
Compressor Design

4:2 compressors are basic components in the design of parallel multipliers. Low power consuming 4:2 compressors can result in a significant reduction of power when realizing power-efficient multipliers in any low power oriented systems. In the area of low power integrated circuit design, adiabatic switching technique has received considerable attention in the recent years. Many adiabatic logic architectures have been reported. In this letter, a low power 4:2 compressor circuit based on the adiabatic switching principle is proposed. When simulated using HSPICE, it was shown that the proposed circuit consumed very much less power than the static CMOS version.

An Opamp-Less PVT Compensation Structure for Ramp Generator Circuit

2020 ◽  
pp. 2150032
Author(s):  
Mohsen Padash ◽  
Mostafa Yargholi ◽  
Maryam Shojaei Baghini
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Feedback Loop ◽  
Cmos Technology ◽  
Compensation Structure ◽  
Ramp Generator ◽  
Generator Circuit ◽  
Low Power Dissipation ◽  
Ramp Signal

Accurate ramp signal, with low power dissipation, is highly demanded, for applications like counter ADC. This paper presents a novel low power ramp generator circuit with a negative feedback loop for compensation of the variations in process, voltage, and temperature (PVT). While using an opamp for PVT compensation has been essential in the previous ramp generator structures, the proposed ramp generator is opamp-less. Derived equations of the proposed ramp generator circuit show that PVT compensation structure works effectively. In addition, the circuit design and simulations were done in TSMC 0.18[Formula: see text][Formula: see text]m CMOS technology. Corner analysis shows that integral non-linearity (INL) of the ramp signal is about 3.7[Formula: see text]mV, for a wide temperature range, while the power dissipation of the circuit is about 1.16[Formula: see text][Formula: see text]W.

scholarly journals An Ultra-Low Power Parity Generator Circuit Based on QCA Technology

2019 ◽  
Vol 2019 ◽  
pp. 1-8 ◽  
Author(s):  
Ismail Gassoumi ◽  
Lamjed Touil ◽  
Bouraoui Ouni ◽  
Abdellatif Mtibaa
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Electrostatic Interactions ◽  
Cmos Technology ◽  
Power Parity ◽  
Ultra Low Power ◽  
Generator Circuit ◽  
Comparison Results ◽  
Low Power Dissipation ◽  
Parity Generator

Quantum-dot cellular automata (QCA) technology is one of the emerging technologies that can be used for replacing CMOS technology. It has attracted significant attention in the recent years due to its extremely low power dissipation, high operating frequency, and a small size. In this study, we demonstrate an n-bit parity generator circuit by utilizing QCA technology. Here, a novel XOR gate is used in the synthesis of the proposed circuit. The proposed gate is based on electrostatic interactions between cells to perform the desired function. The comparison results demonstrate that the designed QCA circuits have advantages compared to other circuits in terms of cell count, area, delay, and power consumption. The QCADesigner software, as widely used QCA circuit design and verification, has been used to implement and to verify all of the designs in this study. Power dissipation has been computed for the proposed circuit using accurate QCAPro power estimator tool.

scholarly journals Nano-Power Low-Dropout Voltage Regulator Circuit in 90-nm CMOS Technology for RF SoC Applications

2021 ◽  
Vol 15 ◽  
pp. 240-248
Author(s):  
Hicham Akhamal ◽  
Mostafa Chakir ◽  
Hatim Ameziane ◽  
Mohammed Akhamal ◽  
Kamal Zared ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Cmos Technology ◽  
System On Chip ◽  
Drop Out ◽  
Voltage Regulator ◽  
Weak Inversion ◽  
Low Power Dissipation ◽  
On Chip ◽  
Ldo Regulator

This paper presents a nano-power Low Drop-Out (LDO) voltage regulator circuit for Radio-Frequency System-on-Chip (RF SoC) applications, this LDO is designed for a smaller dimension due to CMOS technology and in the weak inversion region, can thus be used to minimize power loss of LDO regulator without transientresponse degradation. The proposed structure its low power dissipation make it ideal for RF system-on-chip applications that require low power dissipation under different loading conditions. In order to optimize performance for LDO, the proposed amplifier helps to minimize power of LDO regulators without using any onchip and off-chip compensation capacitors. The output spot noise at 100Hz and 1 kHz are 200nV/sqrt (Hz) and 6nV/sqrt (Hz), respectively. The active area of the circuit is 850 µm2 . The regulator operates with supply voltages from 1.2V to 2V.

Design of (2, 1, N) Parallel Convolutional Encodes for VLSI

2013 ◽  
Vol 321-324 ◽  
pp. 2822-2827 ◽  
Author(s):  
Mao Qiang Duan ◽  
Xiao Li Huang
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Hardware Design ◽  
Cmos Technology ◽  
Shift Register ◽  
Vlsi Implementation ◽  
Parallel Method ◽  
Parallel Circuits ◽  
Low Power Dissipation

The characters of more high speed computing and much less low power dissipation are needed to settle for convolutional encodes. In this paper, we present a parallel method for convolutional encodes with SMIC 0.35μm CMOS technology; hardware design and VLSI implementation of this algorithm are also presented. Use this method, parallel circuits structure can be easily designed, which take on excellent characters of more high speed computing and low power dissipation compared with traditional serial shift register structure for convolutional encodes.

scholarly journals Design of Low Power Multiplexer and De-Multiplexer using Different Adiabatic Logics

2020 ◽  
Vol 9 (1) ◽  
pp. 465-473
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Digital Circuit ◽  
Logic Circuits ◽  
Digital Circuit Design ◽  
Adiabatic Logic ◽  
Low Power Dissipation ◽  
In Series ◽  
Main Factor

In this paper we proposed, design and evaluation of 16:1 Multiplexer and 1:16 Demultiplexer using different adiabatic logics. Power consumption is the main factor in VLSI digital circuit design. Here we have introduced a CMOS-logic based 16:1 Multiplexer and 1:16 De-multiplexer with a low power adiabatic logic. In which we concentrate on the characteristics of the CMOS and adiabatic logics such as 2N2P, 2N-2N2P and Dual sleep. Wherein both 2N2P and 2N2N2P use a cross-coupled transistor structure for adiabatic operation. Adiabatic logic circuits use reverse logic and the power dissipation will be less compared to the CMOS circuits as the inputs are given to the n-type functional tree in 2N2P and 2N2N2P. For dual sleep logic an additional circuit is connected in series with general CMOS circuit known as sleep circuit. we have concentrated on energy recovery and power dissipation, as all these technique results in the low power dissipation. Dualsleep is considered as the best of the all the other adiabatic and traditional logics

scholarly journals Yeo Kiat Seng

2020 ◽  
Author(s):  
Kiat Seng Yeo
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Cmos Technology ◽  
Integrated Circuit Design ◽  
University Of Technology ◽  
Founding Director ◽  
The Republic ◽  
The University ◽  
Technological University

Professor Yeo Kiat Seng received the B.Eng. (EE) in 1993, and Ph.D. (EE) in 1996 both from Nanyang Technological University (NTU), Singapore. Currently, he is Associate Provost (Research and International Relations), Singapore University of Technology and Design (SUTD). Yeo is a widely known authority in low-power RF/mm-wave IC design and a recognized expert in CMOS technology. He was a Member of Board of Advisors of the Singapore Semiconductor Industry Association. Before his appointment at SUTD, Yeo was Associate Chair (Research), Head of Division of Circuits and Systems, Sub-Dean (Student Affairs) and Founding Director of VIRTUS of the School of Electrical and Electronic Engineering at NTU. He has published 9 books, 7 book chapters, over 600 international top-tier refereed journals and conference papers and holds 38 patents. In addition, Yeo holds/held key positions in many international conferences as Advisor, General Chair, Co-General Chair and Technical Chair. In 2009, Yeo was awarded the Public Administration Medal (Bronze) on National Day 2009 by the President of the Republic of Singapore and the Nanyang Alumni Achievement Award by NTU for his outstanding contributions to the university and society. Yeo is an IEEE Fellow for his contributions to low-power integrated circuit design.

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