Skill Needs in VLSI Circuits

1992 ◽  
Vol 6 (1) ◽  
pp. 50-50
Author(s):  
Klaus Wölcken
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Vlsi Design ◽  
Vlsi Circuits ◽  
Academic Institutions ◽  
Directorate General

The forecast need for designers of Very Large Scale Integrated Circuits is described. The article then goes on to outline the support being provided for academic institutions involved with VLSI design training by the European Commission's Directorate General XIII.

Contact Resistance and Methods for its Determination

1982 ◽  
Vol 18 ◽  
Author(s):  
S. Simon Cohen
Keyword(s):  
Integrated Circuits ◽  
Contact Resistance ◽  
Large Scale ◽  
Ohmic Contacts ◽  
Vlsi Circuits ◽  
Single Element ◽  
Large Scale Integration ◽  
Proper Definition ◽  
Definition Of ◽  
Scale Integration

The problem of low resistance ohmic contacts to silicon has been of considerable technological interest. In recent years this problem has received special attention owing to the effect of scaling in very-large-scale integration (VLSI) technology. The field of ohmic contacts to semiconductors comprises two independent parts. First there exists the material science aspect. The choice of a suitable metallization system, the proper semiconductor parameters and the method of the contact formation is not obvious. Then there is the question of the proper definition of the contact resistance and the way it is measured.Several methods for contact resistance determination have been introduced in the past. All seem to have some drawbacks that either limit their usefulness or raise doubts as to their validity in certain situations. We shall discuss the two-, three- and four-terminal resistor methods of measurement. Relevant theoretical considerations will also be included.For conventional integrated circuits with a moderate junction depth of 1–2 μm, aluminum is uniquely suited as a single-element metallization system. However, for VLSI applications it may become obsolete because of several well-defined metallurgical problems. Thus, other metallization systems have to be investigated. We shall briefly discuss some recent data on several other metallization systems. Finally, the problem of size effects on the contact resistance will be discussed. Recent experimental results suggest important clues regarding the development of alternative metallization systems for VLSI circuits and also point to revisions of estimates of achievable design rules.

scholarly journals Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 496 ◽  
Author(s):  
Muhammad Shakir ◽  
Shuoben Hou ◽  
Raheleh Hedayati ◽  
Bengt Gunnar Malm ◽  
Mikael Östling ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuits ◽  
Large Scale ◽  
Extreme Environment ◽  
Design Criterion ◽  
Vlsi Circuits ◽  
Design Flow ◽  
Collector Current ◽  
Threshold Voltage Shift ◽  
Flip Flop

A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta ( β ) and collector current ( I C ) variation of SiC devices as temperature increases. The PDK-based complex digital ICs design flow based on layout, physical verification, and in-house fabrication process will also be demonstrated. Both combinational and sequential circuits have been designed, such as a 720-device ALU and a 520-device 4 bit counter. All the integrated circuits and devices are fully characterized up to 500 °C. The inverter and a D-type flip-flop (DFF) are characterized as benchmark standard cells. The proposed work is a key step towards SiC-based very large-scale integrated (VLSI) circuits implementation for high-temperature applications.

scholarly journals Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits

2017 ◽  
Author(s):  
Vinícius Dos Santos Livramento ◽  
José Luís Güntzel
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Cmos Technology ◽  
Vlsi Circuits ◽  
Consumer Electronics ◽  
Clock Frequency ◽  
Wide Range ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration

The evolution of CMOS technology made possible integrated circuits with billions of transistors assembled into a single silicon chip, giving rise to the jargon Very-Large-Scale Integration (VLSI). VLSI circuits span a wide range class of applications, including Application Specific Circuits and Systems-On-Chip. The latter are responsible for fueling the consumer electronics market, especially in the segment of smartphones and tablets, which are responsible for pushing hardware performance requirements every new generation. The required clock frequency affects the performance of a VLSI circuit and induces timing constraints that must be properly handled by synthesis tools. This thesis focuses on techniques for timing closure of cellbased VLSI circuits, i.e. techniques able to iteratively reduce the number of timing violations until the synthesis of the synchronous digital system reaches the specified target frequency.

Metallization for Very-Large-Scale Integrated Circuits

1981 ◽  
Vol 10 ◽  
Author(s):  
P. B. Ghate
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Vlsi Circuits ◽  
Oxide Semiconductor ◽  
Vlsi Circuit ◽  
Chip Area ◽  
Circuit Performance ◽  
Platinum Silicide ◽  
Silicon Crystals ◽  
Device Structures

Progress in patterning technologies and computer-aided circuit designs have brought us to the threshold of very-large-scale integrated (VLSI) circuits with 100 000 or more devices to be integrated on a silicon chip. In this paper we review thin film applications in the fabrication of contacts and interconnects for VLSI circuits. Device structures suitable for both bipolar and metal/oxide/semiconductor (MOS) VLSI circuit applications tend to have shallow junction depths and contact areas (silicon-metal interfaces) in the 0.2–0.5 μm and 1–2μm2 ranges respectively; also some of the circuits require Schottky barrier diodes. Consumption of silicon in the contact windows needs to be minimized with the use of silicide layers for siliconmetal contacts. The formation and use of platinum silicide layers for bipolar applications are reviewed. Our observations indicate that the carbon and oxygen present in Czochralski-grown silicon crystals interfere in platinum silicide formationand affect the electrical characteristics of the contacts. The use of barrier layers in VLSI metallization is illustrated. The interdependence of film microstructure, electromigration-induced failures and VLSI interconnection reliability is examined. The integration of a large number of components on a VLSI chip with a single level of interconnections consumes more chip area. Long interconnection paths adversely affect circuit performance. Multilevel interconnections (conductor/insulator/conductor) offer an attractive solution to increase the packing density and circuit performance. The application of PtSi/(Ti: W)/(Al-Cu)/SiO2 /(Ti: W)/A1 film layers in the fabrication of a bipolar VLSI circuit with a minimum feature size of 1.25 μm is illustrated. As the complexity of VLSI circuits continues to grow with micron size device structures, three or more levels of interconnections compatible with shallow junctions on the substrates and complex packaging technologies are required. Areas of concern and desirable features in VLSI metallization are summarized.

scholarly journals Crosstalk-Aware Global Routing in VLSI Design by Using a Shuffled Frog-Leaping Algorithm

2020 ◽  
Author(s):  
Apichat Terapasirdsin ◽  
Supaporn Kiattisin
Keyword(s):  
Large Scale ◽  
Vlsi Design ◽  
Vlsi Circuits ◽  
Limiting Factors ◽  
Vlsi Circuit ◽  
Shuffled Frog Leaping Algorithm ◽  
Coupling Capacitance ◽  
Best Value ◽  
Capacitive Effect ◽  
Shuffled Frog Leaping

Nowadays, very large scale integrated (VLSI) circuit technology is developing rapidly. It is necessary to consider many factors related to the VLSI circuit design. Interference is one of the factors that must be considered in high-frequency systems. The parasitic elements become serious limiting factors in the circuit. This research provided a method to reduce crosstalk energy by considering the transition of the signal. Crosstalk is the main capacitive effect which is elected by a high-coupling capacitance between lines. This study considers the wiring path signal with disturbance using the theory of optimization model, assisting in the search of the best sort in signal lines. The technique of a shuffled frog leaping algorithm (SFLA) is being used to search for the best value in arranged signal lines. The result will be minimal noise. The study finds that the arrangement using the SFLA causes only 36.42% of the noise. It was initially evident and 13.06%, when compared with the average all, is born noise value. These techniques can be applied in the design of arranging signal line in the VLSI circuits.

scholarly journals A genetic algorithm approach for global routing of VLSI circuits

2018 ◽  
Vol 7 (2.21) ◽  
pp. 394
Author(s):  
D Ravikumar ◽  
Arun Raaza ◽  
V Devi ◽  
E Gopinathan
Keyword(s):  
Genetic Algorithm ◽  
Cost Function ◽  
Large Scale ◽  
Vlsi Design ◽  
Physical Design ◽  
Vlsi Circuits ◽  
Routing Problem ◽  
Performance Requirements ◽  
Genetic Algorithm Approach ◽  
The Cost

Very Large Scale Integrating (VLSI) design has the objectives of producing the layout for integrating circuits. The currently prevalent submicron regions require innovative, new physical design algorithms. Performance requirements have not seen before, become the significant features of such regions. The last ten years have been witnessing the feature of swelling success of Genetic Algorithms in their application to VLSI physical design. These algorithms are in spot light and the subject matter of study and examination. Routing problem is posed to a cost function which takes care of the total net length, the channel capacity exceedance and crosstalk. The Genetic algorithm is used for optimizing the cost function.  

Some applications of electron beam microanalysis techniques in VLSI process evaluation

1983 ◽  
Vol 41 ◽  
pp. 160-161
Author(s):  
Simon Thomas
Keyword(s):  
Integrated Circuits ◽  
Process Evaluation ◽  
Large Scale ◽  
Technology Development ◽  
Analytical Techniques ◽  
Successful Implementation ◽  
Analysis Of Failures ◽  
Characterization Of Materials ◽  
Circuits Vlsi

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.

Electron microscopy study of reactively sputter-deposited Ti/N films on silicon

1992 ◽  
Vol 50 (2) ◽  
pp. 1362-1363
Author(s):  
V. C. Kannan ◽  
A. K. Singh ◽  
R. B. Irwin ◽  
S. Chittipeddi ◽  
F. D. Nkansah ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Hexagonal Phase ◽  
Microscopy Study ◽  
Electron Microscopy Study ◽  
Process Conditions ◽  
Tin Films ◽  
Wide Range ◽  
Fcc Phase ◽  
Circuits Vlsi

Titanium nitride (TiN) films have historically been used as diffusion barrier between silicon and aluminum, as an adhesion layer for tungsten deposition and as an interconnect material etc. Recently, the role of TiN films as contact barriers in very large scale silicon integrated circuits (VLSI) has been extensively studied. TiN films have resistivities on the order of 20μ Ω-cm which is much lower than that of titanium (nearly 66μ Ω-cm). Deposited TiN films show resistivities which vary from 20 to 100μ Ω-cm depending upon the type of deposition and process conditions. TiNx is known to have a NaCl type crystal structure for a wide range of compositions. Change in color from metallic luster to gold reflects the stabilization of the TiNx (FCC) phase over the close packed Ti(N) hexagonal phase. It was found that TiN (1:1) ideal composition with the FCC (NaCl-type) structure gives the best electrical property.

The Structure and Properties of MoSi2 Thin Film in Mos Process

1980 ◽  
Vol 38 ◽  
pp. 326-327
Author(s):  
C.K. Wu ◽  
P. Chang ◽  
N. Godinho
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
High Performance ◽  
Large Scale ◽  
Process Development ◽  
Structure And Properties ◽  
Metal Silicides ◽  
High Oxidation ◽  
Important Approach ◽  
High Oxidation Resistance

Recently, the use of refractory metal silicides as low resistivity, high temperature and high oxidation resistance gate materials in large scale integrated circuits (LSI) has become an important approach in advanced MOS process development (1). This research is a systematic study on the structure and properties of molybdenum silicide thin film and its applicability to high performance LSI fabrication.

Characterization of Interconnect Defects Using Scanning Thermal Conductivity Microscopy

2004 ◽  
Author(s):  
H.W. Ho ◽  
J.C.H. Phang ◽  
A. Altes ◽  
L.J. Balk
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuits ◽  
Large Scale

Abstract In this paper, scanning thermal conductivity microscopy is used to characterize interconnect defects due to electromigration. Similar features are observed both in the temperature and thermal conductivity micrographs. The key advantage of the thermal conductivity mode is that specimen bias is not required. This is an important advantage for the characterization of defects in large scale integrated circuits. The thermal conductivity micrographs of extrusion, exposed and subsurface voids are presented and compared with the corresponding topography and temperature micrographs.

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