scholarly journals Low Power and High Speed D-Latch Circuit Designs Based on Carbon Nanotube FET

2012 ◽  
Vol 2 (1) ◽  
pp. 12 ◽  
Author(s):  
Neda Talebipoor ◽  
Peiman Keshavarzian ◽  
Behzad Irannejad

In this paper we propose low power and high speed D-latche circuits base on carbon nanotube field effect transistor. D-latches are the important state-holding elements and systems performance enhancement will be achieved by improving the flip-flop latches structure. The circuit designs are simulated by Hspice .In this paper the consumption result of the circuit parameters such as delay, power and PDP for our three different D-latch circuit design in various voltages and different temperatures.

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.


2007 ◽  
Vol 4 (23) ◽  
pp. 731-737 ◽  
Author(s):  
Sung-Chan Kang ◽  
Byung-Hwa Jung ◽  
Bai-Sun Kong
Keyword(s):  

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