Accelerating laser processes with a smart two-dimensional polygon mirror scanner for ultra-fast beam deflection

2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Florian Roessler ◽  
André Streek
Keyword(s):  
Energy Distribution ◽  
Real Time ◽  
Laser Processing ◽  
High Speed ◽  
Beam Deflection ◽  
Two Dimensional ◽  
Heat Accumulation ◽  
Field Programmable ◽  
Drill Holes ◽  
Average Laser

Abstract In laser processing, the possible throughput is directly scaling with the available average laser power. To avoid unwanted thermal damage due to high pulse energy or heat accumulation during MHz-repetition rates, energy distribution over the workpiece is required. Polygon mirror scanners enable high deflection speeds and thus, a proper energy distribution within a short processing time. The requirements of laser micro processing with up to 10 kW average laser powers and high scan speeds up to 1000 m/s result in a 30 mm aperture two-dimensional polygon mirror scanner with a patented low-distortion mirror configuration. In combination with a field programmable gate array-based real-time logic, position-true high-accuracy laser switching is enabled for 2D, 2.5D, or 3D laser processing capable to drill holes in multi-pass ablation or engraving. A special developed real-time shifter module within the high-speed logic allows, in combination with external axis, the material processing on the fly and hence, processing of workpieces much larger than the scan field.

Fifty years of Electronic Hardware Implementations of First and Higher Order Neural Networks

2010 ◽  
pp. 269-285 ◽  
Author(s):  
David R. Selviah ◽  
Janti Shawash
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
High Speed ◽  
Higher Order ◽  
Low Latency ◽  
Real Time Control ◽  
Practical Applications ◽  
Field Programmable ◽  
On Chip ◽  
Electronic Hardware

This chapter celebrates 50 years of first and higher order neural network (HONN) implementations in terms of the physical layout and structure of electronic hardware, which offers high speed, low latency, compact, low cost, low power, mass produced systems. Low latency is essential for practical applications in real time control for which software implementations running on CPUs are too slow. The literature review chapter traces the chronological development of electronic neural networks (ENN) discussing selected papers in detail from analog electronic hardware, through probabilistic RAM, generalizing RAM, custom silicon Very Large Scale Integrated (VLSI) circuit, Neuromorphic chips, pulse stream interconnected neurons to Application Specific Integrated circuits (ASICs) and Zero Instruction Set Chips (ZISCs). Reconfigurable Field Programmable Gate Arrays (FPGAs) are given particular attention as the most recent generation incorporate Digital Signal Processing (DSP) units to provide full System on Chip (SoC) capability offering the possibility of real-time, on-line and on-chip learning.

scholarly journals Real Time Monitoring of Diesel Engine Injector Waveforms for Accurate Fuel Metering and Control

2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
Q. R. Farooqi ◽  
B. Snyder ◽  
S. Anwar
Keyword(s):  
Real Time ◽  
High Speed ◽  
Direct Memory Access ◽  
Operating Conditions ◽  
Start Of Injection ◽  
Field Programmable ◽  
High Speed Data Acquisition ◽  
Correction Table ◽  
High Speed Data ◽  
Injector Pulse

This paper presents the development, experimentation, and validation of a reliable and robust system to monitor the injector pulse generated by an engine control module (ECM) which can easily be calibrated for different engine platforms and then feedback the corresponding fueling quantity to the real-time computer in a closed-loop controller in the loop (CIL) bench in order to achieve optimal fueling. This research utilizes field programmable gate arrays (FPGA) and direct memory access (DMA) transfer capability to achieve high speed data acquisition and delivery. This work is conducted in two stages: the first stage is to study the variability involved in the injected fueling quantity from pulse to pulse, from injector to injector, between real injector stators and inductor load cells, and over different operating conditions. Different thresholds have been used to find out the best start of injection (SOI) threshold and the end of injection (EOI) threshold that capture the injector “on-time” with best reliability and accuracy. Second stage involves development of a system that interprets the injector pulse into fueling quantity. The system can easily be calibrated for various platforms. Finally, the use of resulting correction table has been observed to capture the fueling quantity with highest accuracy.

Realization of Real-Time Transmission of Spectrum Data Based on the uPP Interface of OMAPL138

2014 ◽  
Vol 577 ◽  
pp. 640-643 ◽  
Author(s):  
Jie Feng Wang ◽  
Dong Hui Huang ◽  
Chao Hai Li
Keyword(s):  
Real Time ◽  
High Speed ◽  
Direct Memory Access ◽  
Parallel Port ◽  
The Real ◽  
Spectrum Monitoring ◽  
Time Domain Data ◽  
Field Programmable ◽  
Real Time Transmission ◽  
Spectrum Data

This paper presents a high-speed and multi-thread-safe transmission based on the universal parallel port (uPP) of OMAPL138 and Field Programmable Gate Array (FPGA).With the aid of I/O module used with IOM mini-drivers (GIO module) under DSP/BIOS and internal direct memory access (DMA), this system can obtain a high momentary speed at 300MB/s. This system is designed for the real-time transmission of spectrum data and raw time-domain data which are most important data for monitoring the wireless frequency resource. The real-time transmission of spectrum data has been applied in a spectrum monitoring receiver.

Research on Real-Time Plotting of High-Speed CNC Laser Cutting

2014 ◽  
Vol 1006-1007 ◽  
pp. 340-347
Author(s):  
Qiu Xu Hu ◽  
Yue Tong Xu ◽  
Zheng Tuo Wang ◽  
Meng Yang ◽  
Qing Yuan Wang ◽  
...  
Keyword(s):  
Real Time ◽  
Experimental Research ◽  
Laser Cutting ◽  
High Speed ◽  
Processing Route ◽  
Two Dimensional ◽  
Interpolation Algorithm ◽  
Timing Accuracy ◽  
High Speed Cutting ◽  
Sampling Points

According to the confusion effect of processing route drawing, few sampling points and contradiction between timing accuracy and system fluency of Windows system in high-speed CNC real-time plotting process, this paper presents a method based on Windows environment to achieve real-time plotting goal of the machining contour in high-speed CNC laser cutting process by pretreating G codes and interpolation algorithm improvement. Experimental research was implemented and this method has already been successfully applied to practical production. Comparing to traditional real-time plotting method, this method can not only achieve faster real-time plotting, but also ensure accurate graphic drawing quality and meet the demand of practical circumstances. This method, put forward by the author in addressing real-time plotting problem of laser cutting, can be equally applied to other two-dimensional high-speed cutting occasions.

scholarly journals HARDWARE IMPLEMENTATION OF AN ENCRYPTION FOR ENHANCEMENT DGHV

2019 ◽  
Vol 2 (2) ◽  
pp. 44-57
Author(s):  
Zainab H. Mahmood ◽  
Mahmood K. Ibrahem
Keyword(s):  
Real Time ◽  
High Speed ◽  
Hardware Implementation ◽  
Graphics Processing Unit ◽  
Homomorphic Encryption ◽  
Processing Unit ◽  
Fully Homomorphic Encryption ◽  
Encryption Schemes ◽  
Field Programmable ◽  
Programmable Gate Arrays

In constructing a secure and reliable cloud computing environment, a fully homomorphic encryption (FHE) scheme is conceived as a major cryptographic tool, as it enables arbitrary arithmetic evaluation of a cipher text without revealing the plaintext. However, due to very high of fully homomorphic encryption systems stays impractical and unfit for real-time applications  One way to address this restriction is by using graphics processing unit (GPUs) and field programmable gate arrays (FPGAs) to produce homomorphic encryption schemes. This paper represents the hardware implementation of an encryption for enhancement van Dijk, Gentry, Halevi and Vaikuntanathan’s (DGHV) scheme over the integer (DGHV10) using FPGA technology for high speed computation and real time results. The proposed method was simulated via Vivado system generator tools. Then design systems of fully homomrphic encryption are implemented in an FPGA hardware successfully using NEXYS 4 DDR board with ARTIX 7 XC7A100T FPGA. The Experimental results show that the FPGA- based fully homomorphic encryption system is 63 times faster than the simulation based implementation.

Design of Data Acquisition System Based on FPGA

2011 ◽  
Vol 403-408 ◽  
pp. 1592-1595
Author(s):  
Guo Sheng Xu
Keyword(s):  
Data Processing ◽  
Data Acquisition ◽  
Real Time ◽  
High Speed ◽  
Image Data ◽  
Data Acquisition System ◽  
Acquisition System ◽  
Time Data ◽  
Real Time Processing ◽  
Field Programmable

A new kind of data acquisition system is introduced in this paper, in which the multi-channel synchronized real-time data acquisition under the coordinate control of field-programmable gate array(FPGA) is realized. The design uses field programmable gate arrays(FPGA) for the data processing and logic control. For high speed CCD image data processing, the paper adopts regional parallel processing based on FPGA. The FPGA inner block RAM is used to build high speed image data buffer is put into operation to achieve high speed image data integration and real-time processing. The proposed data acquisition system has characteristics of stable performance, flexible expansion, high real-timeness and integration

FPGA Implementation of a High-Speed Two Dimensional Discrete Wavelet Transform

2013 ◽  
Vol 479-480 ◽  
pp. 508-512
Author(s):  
Chin Fa Hsieh ◽  
Tsung Han Tsai
Keyword(s):  
Wavelet Transform ◽  
Discrete Wavelet Transform ◽  
Real Time ◽  
High Speed ◽  
Critical Path ◽  
Vlsi Architecture ◽  
Image Sensor ◽  
Discrete Wavelet ◽  
Two Dimensional ◽  
Clock Period

This paper proposes high-speed VLSI architecture for implementing a forward two-dimensional discrete wavelet transform (2D DWT). The architecture is based on 2D DWT mathematical formulae. A pipelined scheme is used to increase the clock rate, which allows its critical path to take only one adder delay. The proposed design enables 100% hardware use and faster computing than other 2D DWT architecture. It is easily extended to multilevel decomposition because of its regular structure. It requires N/2 by N/2 clock cycles for k-level analysis of an N by N image. The proposed architecture was coded in VerilogHDL and verified on a real time platform which uses a CMOS image sensor, a field-programmable gate array (FPGA) and a TFT-LCD panel. In the simulation, the design worked with a clock period of 132.38MHz. It can be used as an independent IP core for various real-time applications.

Design and Realization of Embedded High-Speed Image Stabilization Device Base on FPGA+DSP

2012 ◽  
Vol 546-547 ◽  
pp. 1586-1591
Author(s):  
Jie Tao Diao ◽  
Jin Ling Xing ◽  
Hong Qi Yu ◽  
Yi Nan Wang ◽  
Yang Yang
Keyword(s):  
Real Time ◽  
High Speed ◽  
Motion Vector ◽  
High Accuracy ◽  
Image Sequences ◽  
Two Dimensional ◽  
Gray Scale ◽  
Image Stabilization ◽  
Module Design ◽  
Test Result

A design and realization of embedded High-speed image stabilization device is present to remove unwanted shaking phenomena in the image sequences captured by the high-speed industrial camera with 256x256 pixel @1000 frames per second, 8bit, Gray scale. Each module design of the mentioned device is introduced in detail. The interested image sequences are transferred through camera link interface to the device, buffered, preprocessed by an FPGA, and processed by DSP to achieve two-dimensional motion vector which is exported by a digital-to-analog chip. The test result shows that the image stabilization device works stable, real-time, high-accuracy.

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