scholarly journals Maximum Temperature Detection System for Integrated Circuits

2015 ◽  
Vol 66 (2) ◽  
pp. 79-84
Author(s):  
Maciej Frankiewicz ◽  
Andrzej Kos
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Detection System ◽  
Absolute Temperature ◽  
Maximum Temperature ◽  
Dynamic Frequency Scaling ◽  
Temperature Detection ◽  
Measurement Results ◽  
Power Management System ◽  
Dynamic Frequency

Abstract The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

scholarly journals Interband Cascade Photonic Integrated Circuits on Native III-V Chip

Sensors ◽  
2021 ◽  
Vol 21 (2) ◽  
pp. 599
Author(s):  
Jerry R. Meyer ◽  
Chul Soo Kim ◽  
Mijin Kim ◽  
Chadwick L. Canedy ◽  
Charles D. Merritt ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Detection System ◽  
Laser Cavity ◽  
Building Blocks ◽  
Drive Power ◽  
Optical Elements ◽  
Photonic Integrated Circuit ◽  
Cleaved Facets ◽  
On Chip

We describe how a midwave infrared photonic integrated circuit (PIC) that combines lasers, detectors, passive waveguides, and other optical elements may be constructed on the native GaSb substrate of an interband cascade laser (ICL) structure. The active and passive building blocks may be used, for example, to fabricate an on-chip chemical detection system with a passive sensing waveguide that evanescently couples to an ambient sample gas. A variety of highly compact architectures are described, some of which incorporate both the sensing waveguide and detector into a laser cavity defined by two high-reflectivity cleaved facets. We also describe an edge-emitting laser configuration that optimizes stability by minimizing parasitic feedback from external optical elements, and which can potentially operate with lower drive power than any mid-IR laser now available. While ICL-based PICs processed on GaSb serve to illustrate the various configurations, many of the proposed concepts apply equally to quantum-cascade-laser (QCL)-based PICs processed on InP, and PICs that integrate III-V lasers and detectors on silicon. With mature processing, it should become possible to mass-produce hundreds of individual PICs on the same chip which, when singulated, will realize chemical sensing by an extremely compact and inexpensive package.

Thermal-Electrical Co-Optimization of Block-Level Floorplanning in 3D Integrated Circuits

2009 ◽  
Author(s):  
Ankur Jain ◽  
Syed Alam ◽  
Scott Pozder ◽  
Robert E. Jones
Keyword(s):  
Integrated Circuits ◽  
Power Density ◽  
Integrated Circuit ◽  
Thermal Design ◽  
Maximum Temperature ◽  
Design Tools ◽  
Design Constraint ◽  
Trade Offs ◽  
Block Level ◽  
3D Integrated Circuits

While the stacking of multiple strata to produce 3D integrated circuits improves interconnect length and hence reduces power and latency, it also results in the exacerbation of the thermal management challenge due to the increased power density. There is a need for design tools to understand and optimize the trade-off between electrical and thermal design at the device and block level. This paper presents results from thermal-electrical co-optimization for block-level floorplanning in a multi-die 3D integrated circuit. A method for temperature computation based on linearity of the governing energy equation is presented. This method is shown to be faster and more accurate than previously used resistance-network based approaches and full-scale FEM simulations. This method is combined with previously reported electrical delay models for 3D ICs to simultaneously optimize both the maximum temperature and the interconnect length. Results outline the various trade-offs between thermal and electrical considerations. It is shown that co-optimization of thermal and electrical objectives results in a floorplan that is attractive from both perspectives. Constraints placed by the 3D IC manufacturing process on design are outlined, showing that the cheapest manufacturing options may not result in optimal electrical and thermal design. In particular, the wafer-on-wafer bonding process requires the two die to be identical, which results in a severe design constraint, particularly on the thermal goal due to the overlap of high power density blocks. Results presented in this work highlight the need for thermal and electrical co-design in multistrata microelectronics, and for reconciling manufacturing and design considerations in order to develop practical design tools for 3D integrated circuits.

scholarly journals Thermal management of three-dimensional integrated circuits with special structures

2021 ◽  
pp. 109-109
Author(s):  
Kang-Jia Wang ◽  
Cui-Ling Li
Keyword(s):  
Temperature Distribution ◽  
Integrated Circuits ◽  
Heat Source ◽  
Thermal Management ◽  
Integrated Circuit ◽  
Three Dimensional ◽  
Numerical Approach ◽  
Optimal Structure ◽  
Maximum Temperature ◽  
Three Dimensional Integrated Circuit

Different stacked structures affect greatly the temperature distribution of a three-dimensional integrated circuit(3-D IC), and an optimal structure is much needed to reduce the maximal temperature. This paper suggests a numerical approach to such structures with different heat source distributions. The results show that an optimal stacked structure can reduce the maximum temperature by 8.7?C.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

Micromechanics Measurements Applied to Integrated Circuit Microelectronics

1997 ◽  
Vol 473 ◽  
Author(s):  
David R. Clarke
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Fracture Resistance ◽  
Interface Fracture ◽  
New Techniques ◽  
Fracture Properties ◽  
Engineered Structures ◽  
Mechanical And Fracture Properties ◽  
Interconnect Lines ◽  
Metallic Interconnect

ABSTRACTAs in other engineered structures, fracture occasionally occurs in integrated microelectronic circuits. Fracture can take a number of forms including voiding of metallic interconnect lines, decohesion of interfaces, and stress-induced microcracking of thin films. The characteristic feature that distinguishes such fracture phenomena from similar behaviors in other engineered structures is the length scales involved, typically micron and sub-micron. This length scale necessitates new techniques for measuring mechanical and fracture properties. In this work, we describe non-contact optical techniques for probing strains and a microscopic “decohesion” test for measuring interface fracture resistance in integrated circuits.

Nanofabricated SiO2-Si-SiO2 Resonant Tunneling Diodes

2000 ◽  
Vol 631 ◽  
Author(s):  
J. G. Fleming ◽  
E. Chow ◽  
S.-Y. Lin
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Resonant Tunneling ◽  
Resonant Tunneling Diodes ◽  
Resonance Tunneling ◽  
Tunneling Diodes

ABSTRACTResonance Tunneling Diodes (RTDs) are devices that can demonstrate very highspeed operation. Typically they have been fabricated using epitaxial techniques and materials not consistent with standard commercial integrated circuits. We report here the first demonstration of SiO2-Si-SiO2 RTDs. These new structures were fabricated using novel combinations of silicon integrated circuit processes.

The Radio Probe™: A New Measurement Tool for High Speed Integrated Circuits

2005 ◽  
Author(s):  
Mark Kimball
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Attenuation Factor ◽  
Cost Effective ◽  
Frequency Measurement ◽  
Single Frequency ◽  
Measurement Tool ◽  
Probe Design ◽  
Differential Measurement

Abstract This article presents a novel tool designed to allow circuit node measurements in a radio frequency (RF) integrated circuit. The discussion covers RF circuit problems; provides details on the Radio Probe design, which achieves an input impedance of 50Kohms and an overall attenuation factor of 0 dB; and describes signal to noise issues in the output signal, along with their improvement techniques. This cost-effective solution incorporates features that make it well suited to the task of differential measurement of circuit nodes within an RF IC. The Radio Probe concept offers a number of advantages compared to active probes. It is a single frequency measurement tool, so it complements, rather than replaces, active probes.

A Technique for Reliably Preparing Full-Length Metallographic Cross-Sections of Integrated Circuit Bond Wires

2006 ◽  
Author(s):  
Carl Nail
Keyword(s):  
Integrated Circuits ◽  
High Precision ◽  
Cross Sections ◽  
Integrated Circuit ◽  
Radiographic Analysis ◽  
Good Resolution ◽  
Metallographic Preparation ◽  
Bond Wires ◽  
Darkfield Imaging ◽  
Bond Wire

Abstract To overcome the obstacles in preparing high-precision cross-sections of 'blind' bond wires in integrated circuits, this article proposes a different technique that generates reliable, repeatable cross-sections of bond wires across most or all of their lengths, allowing unencumbered and relatively artifact-free analysis of a given bond wire. The basic method for cross-sectioning a 'blind' bond wire involves radiographic analysis of the sample and metallographic preparation of the sample to the plane of interest. This is followed by tracking the exact location of the plane on the original radiograph using a stereomicroscope and finally darkfield imaging in which the wire is clearly visible with good resolution.

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