The Radio Probe™: A New Measurement Tool for High Speed Integrated Circuits

2005 ◽  
Author(s):  
Mark Kimball
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Attenuation Factor ◽  
Cost Effective ◽  
Frequency Measurement ◽  
Single Frequency ◽  
Measurement Tool ◽  
Probe Design ◽  
Differential Measurement

Abstract This article presents a novel tool designed to allow circuit node measurements in a radio frequency (RF) integrated circuit. The discussion covers RF circuit problems; provides details on the Radio Probe design, which achieves an input impedance of 50Kohms and an overall attenuation factor of 0 dB; and describes signal to noise issues in the output signal, along with their improvement techniques. This cost-effective solution incorporates features that make it well suited to the task of differential measurement of circuit nodes within an RF IC. The Radio Probe concept offers a number of advantages compared to active probes. It is a single frequency measurement tool, so it complements, rather than replaces, active probes.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

scholarly journals Integrated Dual-DFB PIC for High-Purity THz Carrier Generation Enabling Ultrafast THz Wireless Communications

2021 ◽  
Author(s):  
Shi Jia ◽  
Mu-Chieh Lo ◽  
Lu Zhang ◽  
Oskars Ozolins ◽  
Aleksejs Udalcovs ◽  
...  
Keyword(s):  
Wireless Communications ◽  
Integrated Circuits ◽  
High Purity ◽  
High Speed ◽  
Single Channel ◽  
Cost Effective ◽  
Long Distance ◽  
Practical Applications ◽  
Integrated Cost ◽  
Thz Power

Abstract With the explosive growth of global wireless data traffic, the Terahertz band (0.3–10 THz) is promising for ultrafast wireless communications, due to the enormous available bandwidth [1]. Photonic generation of THz carriers displays extremely large tunable range and modulation bandwidth, making it nearly ideal for THz communications. However, the current photonics-based THz carrier generators are based on discrete bulky components [2] with high cost and energy consumption, which hinder them from practical applications. Here, we present an injection-locked heterodyne source based on generic foundry-fabricated photonic integrated circuits (PIC) attached to a photo-mixing uni-travelling carrier photodiode (UTC-PD), generating high-purity THz carriers for high-speed and long-distance wireless communication. The generated THz carrier can span from 0 to 1.4 THz, determined by the tunable wavelength spacing between the two distributed feedback (DFB) modes within the range 0-10.7 nm. We show that a generated 0.4 THz carrier transmits a record-high single-channel net rate of 131 Gbit/s over 10.7 m of wireless distance with only − 24 dBm emitted THz power, by employing 16-QAM-OFDM modulation and a nonlinear equalization technique. To the best of our knowledge, this is the highest data rate for a single-channel THz wireless transmission and requires the lowest THz power/bitrate/distance. The scheme of the monolithic dual-DFB PIC based THz generation shows a great potential for fully integrated, cost-effective and energy-efficient THz transmitters.

scholarly journals Architecture and implementation of a high frame-rate stereo vision system

2021 ◽  
Author(s):  
Jamin Islam
Keyword(s):  
Integrated Circuits ◽  
Stereo Vision ◽  
High Speed ◽  
Vision System ◽  
Low Cost ◽  
Cost Effective ◽  
Frame Rate ◽  
Superior Performance ◽  
High Frame Rate ◽  
Stereo Vision System

For the purpose of autonomous satellite grasping, a high-speed, low-cost stereo vision system is required with high accuracy. This type of system must be able to detect an object and estimate its range. Hardware solutions are often chosen over software solutions, which tend to be too slow for high frame-rate applications. Designs utilizing field programmable gate arrays (FPGAs) provide flexibility and are cost effective versus solutions that provide similar performance (i.e., Application Specific Integrated Circuits). This thesis presents the architecture and implementation of a high frame-rate stereo vision system based on an FPGA platform. The system acquires stereo images, performs stereo rectification and generates disparity estimates at frame-rates close to 100 fpSi and on a large-enough FPGA, it can process 200 fps. The implementation presents novelties in performance and in the choice of the algorithm implemented. It achieves superior performance to existing systems that estimate scene depth. Furthermore, it demonstrates equivalent accuracy to software implementations of the dynamic programming maximum likelihood stereo correspondence algorithm.

scholarly journals Passivity Preserving Model Order Reduction Using the Reduce Norm Method

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 964
Author(s):  
Namra Akram ◽  
Mehboob Alam ◽  
Rashida Hussain ◽  
Asghar Ali ◽  
Shah Muhammad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Model Order Reduction ◽  
High Speed ◽  
Order Reduction ◽  
Reliable Operation ◽  
Model Order ◽  
Reduced Order ◽  
Reduction Methods ◽  
On Chip

Modeling and design of on-chip interconnect, the interconnection between the components is becoming the fundamental roadblock in achieving high-speed integrated circuits. The scaling of interconnect in nanometer regime had shifted the paradime from device-dominated to interconnect-dominated design methodology. Driven by the expanding complexity of on-chip interconnects, a passivity preserving model order reduction (MOR) is essential for designing and estimating the performance for reliable operation of the integrated circuit. In this work, we developed a new frequency selective reduce norm spectral zero (RNSZ) projection method, which dynamically selects interpolation points using spectral zeros of the system. The proposed reduce-norm scheme can guarantee stability and passivity, while creating the reduced models, which are fairly accurate across selected narrow range of frequencies. The reduced order results indicate preservation of passivity and greater accuracy than the other model order reduction methods.

Flip Chip Underfill RF Characterization

2019 ◽  
Vol 2019 (1) ◽  
pp. 000243-000247
Author(s):  
Robert B. Paul ◽  
A. Ege Engin ◽  
Jerry Aguirre
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Flip Chip ◽  
Power Integrity ◽  
Cavity Resonators ◽  
Dielectric Characterization ◽  
Noise Coupling ◽  
Solder Bumps ◽  
Underfill Material

Abstract To develop reliable high-speed packages, characterization of the underfill material used in the flip-chip process has become of greater importance. The underfill, typically an epoxy resin-based material, offers thermal and structural benefits for the integrated circuit (IC) on package. With so many inputs and outputs (IOs) in close proximity to one another, the integrated circuits on package can have unexpected signal and power integrity issues. Furthermore, chip packages can support signals only up to the frequency where noise coupling (e.g., crosstalk, switching noise, etc.) leads to the malfunctioning of the system. Vertical interconnects, such as vias and solder bumps, are major sources of noise coupling. Inserting ground references between every signal net is not practical. For the solder bumps, the noise coupling depends on the permittivity of the underfill material. Therefore, characterizing the permittivity of the underfill material helps in predicting signal and power integrity issues. Such liquid or semi-viscous materials are commonly characterized from a simple fringe capacitance model of an open-ended coaxial probe immersed in the material. The open-ended coaxial method, however, is not as accurate as resonator-based methods. There is a need for a methodology to accurately extract the permittivity of liquid or semi-viscous materials at high frequencies. The proposed method uses solid walled cavity resonators, where the resonator is filled with the underfill material and cured. Dielectric characterization is a complex process, where the physical characteristics of the cavities must be known or accurately measured. This includes the conductivity of the conductors, roughness of the conductors, the dimensions of the cavity, and the port pin locations. This paper discusses some of the challenges that are encountered when characterizing dielectrics with cavity resonators. This characterization methodology can also be used to characterize other materials of interest.

A TOTAL-DOSE HARDENING-BY-DESIGN APPROACH FOR HIGH-SPEED MIXED-SIGNAL CMOS INTEGRATED CIRCUITS

2004 ◽  
Vol 14 (02) ◽  
pp. 367-378 ◽  
Author(s):  
NATHAN NOWLIN ◽  
JOHN BAILEY ◽  
BOB TURFLER ◽  
DAVE ALEXANDER
Keyword(s):  
Integrated Circuits ◽  
Total Dose ◽  
Integrated Circuit ◽  
High Speed ◽  
Mixed Signal ◽  
Cmos Integrated Circuit ◽  
Ieee 1394 ◽  
Interface Chip ◽  
Signal Interface ◽  
Radiation Tolerant

This paper describes design choices and tradeoffs made when designing total-dose hardness into an advanced CMOS integrated circuit. Closed geometry transistors are described and compared, emphasizing their radiation tolerant performance. Speed and area tradeoffs incurred in circuit design when using such closed geometry transistors are illustrated in the design of an advanced IEEE 1394 cable physical layer mixed-signal interface chip.

scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

Gallium arsenide electronics in the marketplace

1992 ◽  
Vol 70 (10-11) ◽  
pp. 943-945
Author(s):  
Paul R. Jay.
Keyword(s):  
Gallium Arsenide ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Large Scale ◽  
Low Cost ◽  
Logic Gates ◽  
Process Technology ◽  
Maximum Benefit ◽  
Technological Developments

The last few years have seen a significant emergence of real product applications using gallium arsenide metal semi-conductor field effect transistor technology. These applications range from large volume consumer markets based on small low-cost GaAs integrated circuits to high-end supercomputer products using very large scale integrated GaAs chips containing up to 50 000 logic gates. This situation represents substantial advances in many areas: materials technology, device and integrated circuit process technology, packaging and high speed testing, as well as appropriate system design to obtain maximum benefit from the GaAs technology. This paper reviews some recent commercial successes, and considers commonalities existing between them in the context of recent technological developments.

scholarly journals Performance Efficient Alu using Finfet

2019 ◽  
Vol 8 (4) ◽  
pp. 11449-11455
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Power Analysis ◽  
High Speed ◽  
Power Saving ◽  
Arithmetic Functions ◽  
Power Efficient ◽  
Logical Unit ◽  
Simulation Results ◽  
Logical Functions

According to the prophecy of Moore, the concentration of transistors in an integrated circuit doubles every two years. But this is limited by the technologies used in the fabrication of integrated circuits, as the systems are scaled down. FinFET technology aims to combat this challenge. The construction of power efficient high speed Arithmetic & Logical Unit (ALU) using FinFET technology is proposed in this paper. Proposed FinFET based ALU is designed with arithmetic functions like high speed addition, multiplication and logical functions such as AND and XOR. Simulation results of the proposed power efficient high speed FinFET ALU proves to be better with a power saving of 80.5%. FinFET has the advantage of providing low power without compromising on the Performance. The power analysis for ALU is done using CADENCE-VIRTUOSO, which is known for its accuracy.

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