Fault tolerant Automotive CAN Control Embedded System

The embedded system-on-a-chip (SoC), that integrates heterogeneous processors with variation in coherence protocol, adds complexity in maintaining coherency in the data caches. It further complicates the task of coherence verification in such systems. This work targets effective solution for coherence verification in heterogeneous chip multiprocessors (CMPs) through introduction of highly efficient verification unit. It is developed around the modeling tool of cellular automaton (CA) invented by von Neumann in 1950s. The modular and cascadable structure of CA ensures high scalability and robustness in the proposed design. A CA segment is employed to analyze the states of a data block in different private caches of a heterogeneous processor cluster and to verify inconsistencies, if any, within the cluster. The outcomes of coherence verification for clusters are analyzed by the CA resulted out of augmentation of the CA segments. On the other hand, in this work, we further propose a CA-based coherence protocol processor (PP), which caters the need for determining the state of a data block with high accuracy. The PP designed for the heterogeneous CMPs, while computing the states of za block on every transaction (read/write), can capture defects, if any, and thereby realizes a fault-tolerant PP without introduction of additional hardware logic.

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Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded System

International Journal of Reconfigurable Computing ◽

10.1155/2014/806237 ◽

2014 ◽

Vol 2014 ◽

pp. 1-8 ◽

Cited By ~ 2

Author(s):

Mohsin Amin ◽

Muhammad Shakir ◽

Aqib Javed ◽

Muhammad Hassan ◽

Syed Ali Raza

Keyword(s):

Embedded System ◽

Real Time ◽

Design Methodology ◽

Fault Tolerant ◽

Low Cost ◽

Design Constraints ◽

Hardware Overhead ◽

And Performance ◽

The Given

We are proposing a design methodology for a fault tolerant homogeneous MPSoC having additional design objectives that include low hardware overhead and performance. We have implemented three different FT methodologies on MPSoCs and compared them against the defined constraints. The comparison of these FT methodologies is carried out by modelling their architectures in VHDL-RTL, on Spartan 3 FPGA. The results obtained through simulations helped us to identify the most relevant scheme in terms of the given design constraints.

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A Software Architecture for Handling Complex Critical Section Constraints on Multiprocessors in a Fault-Tolerant Real-Time Embedded System

10.29007/brkj ◽

2019 ◽

Author(s):

Jia Xu

Keyword(s):

Fault Tolerance ◽

Embedded System ◽

Software Architecture ◽

Real Time ◽

Data Structures ◽

Fault Tolerant ◽

Critical Section ◽

Shared Data ◽

Time Task ◽

Critical Sections

In a real-time embedded system which uses a primary and an alternate for each real-time task to achieve fault tolerance, there is a need to allow both primaries and alternates to have critical sections/segments in which shared data structures can be read and updated while guaranteeing that the execution of any part of one critical section will not be interleaved with or overlap with the execution of any part of a critical section belonging to some other primary or alternate which reads and writes on those shared data structures. In this paper a software architecture is presented which effectively handles critical section constraints where both primaries and alternates may have critical sections which can either overrun or underrun, while still guaranteeing that all primaries or alternates that do not overrun will always meet their deadlines while keeping the shared data in a consistent state on a multiprocessor in a fault tolerant real-time embedded system.

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