berger code
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2018 ◽  
Vol 39 (11) ◽  
pp. 115001
Author(s):  
G. Prasad Acharya ◽  
M. Asha Rani

Author(s):  
G. Prasad Acharya ◽  
M. Asha Rani

In this paper, we propose an approach to detect the temporary faults induced by an environmental phenomenon called single event upset (SEU). Berger code based self-checking checkers provides an online detection of faults in digital circuits as well as in memory arrays. In this work, a concurrent Berger code based online self- testable methodology is proposed and integrated in 32-bit DLX Reduced Instruction Set Computer (RISC) processor on a single silicon chip. The proposed methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self- testing to detect temporary faults.


2010 ◽  
Vol 57 (10) ◽  
pp. 777-781 ◽  
Author(s):  
Stanisław J. Piestrak ◽  
Sebastien Pillement ◽  
Olivier Sentieys

2010 ◽  
Vol 14 (8) ◽  
pp. 761-763
Author(s):  
Stanislaw J. Piestrak ◽  
Sebastien Pillement ◽  
Olivier Sentieys

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