DIRECT OBSERVATION OF INTERFACE TRAPS IN OMVPE-GROWN SELECTIVELY AlGaAs/GaAs HETEROSTRUCTURE USING MODIFIED DLTS

1985 ◽  
Vol 56 ◽  
Author(s):  
M. TAKIKAWA ◽  
T. OOHORI ◽  
K. KASAI ◽  
J. KOMENO ◽  
A. SHIBATOMI
Keyword(s):  
Electrical Properties ◽  
Direct Observation ◽  
Drain Current ◽  
Current Transient ◽  
Interface Trap ◽  
Interface Traps ◽  
Gate Bias ◽  
Fitting Procedure ◽  
Bias Pulse ◽  
Positive Peak

AbstractBy using a DLTS technique, we measured the drain current transient from a gate bias pulse for a HEMT. Two negative peaks and one positive peak were observed. From the analysis of the spectra, we found that the positive peak was due to the interface trap. The density of the interface trap was determined from a DLTS fitting procedure. The effect of the interface traps on the electrical properties of the heterostructure are discussed.

TCAD Modeling of a 1200 V SiC MOSFET

2018 ◽  
Vol 924 ◽  
pp. 689-692
Author(s):  
K. Lee ◽  
Benedetto Buono ◽  
Martin Domeij ◽  
Jimmy Franchi
Keyword(s):  
Surface Roughness ◽  
Room Temperature ◽  
Transfer Characteristic ◽  
Interface Trap ◽  
Coulomb Scattering ◽  
Interface Traps ◽  
Gate Bias ◽  
Channel Mobility ◽  
Output Characteristics ◽  
Increasing Temperature

In this work, TCAD modeling of a 1200 V SiC MOSFET is presented. The main focus is on modeling of the channel mobility, and the Coulomb scattering by interface traps and surface roughness are therefore included. For the Coulomb scattering, the interface trap profiles have been extrapolated from the subthreshold characteristics at room temperature, whereas the scattering due to surface roughness has been fitted by comparing to the transfer characteristics at high gate bias. A comparison with measurements for the transfer characteristic and the output characteristic is also presented. Results show that the reduction of the threshold voltage with increasing temperature and the temperature dependence of the output characteristics are properly modeled.

Development of 1200 V, 3.7 mΩ-cm2 4H-SiC DMOSFETs for Advanced Power Applications

2012 ◽  
Vol 717-720 ◽  
pp. 1059-1064 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Lin Cheng ◽  
Sarit Dhar ◽  
Craig Capell ◽  
Charlotte Jonas ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Voltage Drop ◽  
Drain Current ◽  
Subthreshold Swing ◽  
Active Area ◽  
Gate Bias ◽  
Forward Voltage ◽  
Recent Developments ◽  
Forward Voltage Drop

We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.

Influence of Chemical Modification on the Electrical Properties of Si Nanowire Arrays

2010 ◽  
Vol 160-162 ◽  
pp. 1331-1335 ◽  
Author(s):  
Chuan Bo Li ◽  
Kristel Fobelets ◽  
S.N. Syed Jalal ◽  
Wei A. Ng ◽  
Zahid A.K. Durrani
Keyword(s):  
Electrical Conductivity ◽  
Electrical Property ◽  
Electrical Properties ◽  
Chemical Modification ◽  
Nanowire Array ◽  
Noise Measurement ◽  
Nanowire Arrays ◽  
Interface Traps ◽  
Si Nanowire ◽  
Si Nanowire Array

The influence of the chemical modification on the electrical property of Si nanowire array was studied. It is found that H-terminated Si nanowire has a better electrical conductivity while OH-passivation could increase their resistance. It is believed that the introducing of OH group on the surface nanowire increases the interface traps and it is confirmed by our 1/f noise measurement.

Impact of interface trap charges on Junctionless double and triple metal gate High-k Gate All Around Nanowire FET based Alzheimer Biosensor

2021 ◽  
Author(s):  
Rishu Chaujar ◽  
Mekonnen Getnet Yirak
Keyword(s):  
Threshold Voltage ◽  
Positive Impact ◽  
Drain Current ◽  
Interface Trap ◽  
Metal Gate ◽  
High K ◽  
Current Threshold ◽  
Subthreshold Voltage ◽  
Output Characteristics ◽  
The Impact

Abstract In this work, junctionless double and triple metal gate high-k gate all around nanowire field-effect transistor-based APTES biosensor has been developed to study the impact of ITCs on device sensitivity. The analytical results were authenticated using ‘‘ATLAS-3D’’ device simulation tool. Effect of different interface trap charge on the output characteristics of double and triple metal gate high-k gate all around junctionless NWFET biosensor was studied. Output characteristics, like transconductance, output conductance,drain current, threshold voltage, subthreshold voltage and switching ratio, including APTES biomolecule, have been studied in both devices. 184% improvement has been investigated in shifting threshold voltage in a triple metal gate compared to a double metal gate when APTES biomolecule immobilizes on the nanogap cavity region under negative ITCs. Based on this finding, drain off-current ratio and shifting threshold voltage were considered as sensing metrics when APTES biomolecule immobilizes in the nanogap cavity under negative ITCs which is significant for Alzheimer's disease detection. We signifies a negative ITC has a positive impact on our proposed biosensor device compared to positive and neutral ITCs.

5A 1300V Trenched and Implanted 4H-SiC Vertical JFET

2012 ◽  
Vol 229-231 ◽  
pp. 824-827 ◽  
Author(s):  
Gang Chen ◽  
Xiao Feng Song ◽  
Song Bai ◽  
Li Li ◽  
Yun Li ◽  
...  
Keyword(s):  
Ohmic Contact ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Vertical Channel ◽  
Drain Current ◽  
Gate Bias ◽  
Blocking Voltage ◽  
Drain Bias ◽  
Effect Transistor ◽  
Lift Off

A silicon carbide (SiC) vertical channel junction field effect transistor (VJFET) was fabricated based on in-house SiC epitaxial wafer with lift-off trenched and implanted method. Its blocking voltage exceeds 1300V at gate bias VG = -6V and forward drain current is in excess of 5A at gate bias VG = 3V and drain bias VD = 3V. The SiC VJFET device’s current density is 240A/cm2 at VG= 3V and VD = 3V, with related specific on-resistance 8.9mΩ•cm2. Further analysis reveals that the on-resistance depends greatly on ohmic contact resistance and the bonding spun gold. The specific on-resistance can be further reduced by improving the doping concentration of SiC channel epilayer and the device’s ohmic contact.

Research on Threshold Voltage Instability in SiC MOSFET Devices with Precision Measurement

2019 ◽  
Vol 954 ◽  
pp. 133-138
Author(s):  
Ao Liu ◽  
Song Bai ◽  
Run Hua Huang ◽  
Tong Tong Yang ◽  
Hao Liu
Keyword(s):  
Threshold Voltage ◽  
Precision Measurement ◽  
Gate Dielectric ◽  
Interface Traps ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Experimental Platform ◽  
Bias Stress ◽  
Voltage Instability ◽  
Voltage Drift

The mechanism of threshold voltage shift was studied. It is believed that the instability in threshold voltage during gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. New experimental platform was designed and built successfully. When positive stress or negative stress is applied to the gate, the change of threshold voltage occur immediately. After stress removal, the recovery of the threshold voltage occur soon. The change and recovery of threshold voltage are very sensitive to time. In order to get accurate threshold voltage drift data after high-temperature gate bias experiment, test of threshold voltage must be carried out immediately after the experiment.

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