Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho
Keyword(s):  
Packing Density ◽  
Propagation Delay ◽  
Single Chip ◽  
Crosstalk Noise ◽  
Metal Line ◽  
Total Delay ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

Materials Issues and Characterization of Low-k Dielectric Materials

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 49-54 ◽  
Author(s):  
E. Todd Ryan ◽  
Andrew J. McKerrow ◽  
Jihperng Leu ◽  
Paul S. Ho
Keyword(s):  
Process Integration ◽  
Dielectric Materials ◽  
Propagation Delay ◽  
Thermomechanical Properties ◽  
General Criterion ◽  
Crosstalk Noise ◽  
Total Delay ◽  
Interlayer Dielectrics ◽  
Performance Improvements ◽  
And Performance

Continuing improvement in device density and performance has significantly affected the dimensions and complexity of the wiring structure for on-chip interconnects. These enhancements have led to a reduction in the wiring pitch and an increase in the number of wiring levels to fulfill demands for density and performance improvements. As device dimensions shrink to less than 0.25 μm, the propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant. Accordingly the interconnect delay now constitutes a major fraction of the total delay limiting the overall chip performance. Equally important is the processing complexity due to an increase in the number of wiring levels. This inevitably drives cost up by lowering the manufacturing yield due to an increase in defects and processing complexity.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILDs) and alternative architectures have surfaced to replace the current Al(Cu)/SiO2 interconnect technology. These alternative architectures will require the introduction of low-dielectric-constant k materials as the interlayer dielectrics and/or low-resistivity conductors such as copper. The electrical and thermomechanical properties of SiO2 are ideal for ILD applications, and a change to material with different properties has important process-integration implications. To facilitate the choice of an alternative ILD, it is necessary to establish general criterion for evaluating thin-film properties of candidate low-k materials, which can be later correlated with process-integration problems.

Sol–gel deposited xerogel, aerogel and porogen based porous low-k thin films: A comparative investigation

2021 ◽  
pp. 2140019
Author(s):  
Swati Gupta ◽  
Anil Gaikwad ◽  
Ashok Mahajan ◽  
Lin Hongxiao ◽  
He Zhewei
Keyword(s):  
Dielectric Constant ◽  
Sol Gel ◽  
Comparative Investigation ◽  
Crosstalk Noise ◽  
Nanoelectronic Devices ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Xerogel Films ◽  
Low K ◽  
Porosity Percentage

Low dielectric constant (Low-[Formula: see text]) films are used as inter layer dielectric (ILD) in nanoelectronic devices to reduce interconnect delay, crosstalk noise and power consumption. Tailoring capability of porous low-[Formula: see text] films attracted more attention. Present work investigates comparative study of xerogel, aerogel and porogen based porous low-[Formula: see text] films. Deposition of SiO2 and incorporation of less polar bonds in film matrix is confirmed using Fourier Transform Infra-Red Spectroscopy (FTIR). Refractive indices (RI) of xerogel, aerogel and porogen based low-[Formula: see text] films observed to be as low as 1.25, 1.19 and 1.14, respectively. Higher porosity percentage of 69.46% is observed for porogen-based films while for shrinked xerogel films, it is lowered to 45.47%. Porous structure of low-[Formula: see text] films has been validated by using Field Emission Scanning Electron Microscopy (FE-SEM). The pore diameters of porogen based annealed samples were in the range of 3.53–25.50 nm. The dielectric constant ([Formula: see text]) obtained from RI for xerogel, aerogel and porogen based films are 2.58, 2.20 and 1.88, respectively.

Siloxane Polymers as Low Dielectric Materials for Microelectronics

1995 ◽  
Vol 390 ◽  
Author(s):  
C. P. Wong
Keyword(s):  
Dielectric Constant ◽  
Three Dimensional ◽  
Signal Propagation ◽  
Dielectric Materials ◽  
Propagation Delay ◽  
Dimensional Structure ◽  
Low Dielectric Constant ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
High Dielectric

ABSTRACTA modem VLSI device is a complicated three-dimensional structure that consists of multilayer metallization conductor lines which are separated with interlayer-dielectrics as insulation. This VLSI technology drives the IC device into sub-micron feature size that operates at ultra-fast speed (in excess of > 100 MHz). Passivation and interlayer dielectric materials are critical to the device performance due to the conductor signal propagation delay of the high dielectric constant of the material. Low dielectric constant materials are the preferred choice of materials for this reasons. These materials, such as Teflon® and siloxanes (silicones), are desirable because of their low dielectric constant (∈1) = 2.0, 2.7, respectively. This paper describes the use of a low dielectric constant siloxane polymer (silicone) as IC devices passivation layer material, its chemistry, material processes and reliability testing.

Intrinsic low dielectric behaviour of a highly thermally stable Sr-based metal–organic framework for interlayer dielectric materials

2014 ◽  
Vol 2 (19) ◽  
pp. 3762-3768 ◽  
Author(s):  
Muhammad Usman ◽  
Cheng-Hua Lee ◽  
Dung-Shing Hung ◽  
Shang-Fan Lee ◽  
Chih-Chieh Wang ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Metal Organic Framework ◽  
Dielectric Materials ◽  
Low Dielectric Constant ◽  
Water Molecules ◽  
Compound A ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Metal Organic ◽  
Organic Framework

A Sr-based metal–organic framework exhibits an intrinsic low dielectric constant after removing the water molecules. A low dielectric constant and high thermal stability make this compound a candidate for use as a low-k material.

New Carbon-bridged Hybrid Polymers for Low-k Materials

2005 ◽  
Vol 863 ◽  
Author(s):  
Bum-Gyu Choi ◽  
Byung Ro Kim ◽  
Myung-Sun Moon ◽  
Jung-Won Kang ◽  
Min-Jin Ko
Keyword(s):  
Mechanical Properties ◽  
Hybrid Materials ◽  
Chemical Mechanical Planarization ◽  
Sol Gel ◽  
Dielectric Constants ◽  
Metal Line ◽  
Inorganic Hybrid ◽  
Low Dielectric ◽  
Continuous Stiffness Measurement ◽  
Low K

AbstractReducing interline capacitance and line resistance is required to minimize RC delays, reduce power consumption and crosstalk below 100nm node technology. For this purpose, various inorganic- and organic polymers have been tested to reduce dielectric constants in parallel with the use of copper as metal line. Lowering the dielectric constants, in particular, causes the detrimental effect on mechanical properties, and then leads to film damage and/or delamination during chemical-mechanical planarization CMP) or repeated thermal cure cycles. To overcome this issue, new carbon-bridged hybrid materials synthesized by organometallic silane precursors and sol-gel reaction are proposed.In this work, we have developed new organic-inorganic hybrid low-k dielectrics with linear or cyclic carbon bridged structures. The differently bridged carbon structures were formed by a controlled reaction. 1H NMR, 29Si NMR analysis and GC/MSD analysis were conducted for the structural characterization of new hybrid low-k dielectric. The mechanical and dielectric properties of these hybrid materials were characterized by using nanoindentation with continuous stiffness measurement and Al dot MIS techniques. The results indicated that these organic-inorganic hybrid materials were very promising polymers for low-k dielectrics that had low dielectric constants with high thermal and mechanical properties. It has been also demonstrated that electrical and mechanical properties of the hybrid films could be tailored by copolymerization with PMSSQ and through the introduction of porogen.

A Multilevel Metal Interconnect Technology with Intra-Metal Air-Gap for Quarter-Micron-and-Beyond High-Performance Processes

2000 ◽  
Vol 612 ◽  
Author(s):  
Mark Lin ◽  
Chun-Yen Chang ◽  
Tiao-Yuan Huang ◽  
Mout-Lim Lin ◽  
Horng-Chin Lin
Keyword(s):  
Delay Time ◽  
High Performance ◽  
Air Gap ◽  
Low Dielectric Constant ◽  
Low Dielectric ◽  
Turn Around Time ◽  
Fringing Capacitance ◽  
Rc Delay ◽  
Interconnect Technology ◽  
Density Plasma

AbstractA multilevel metal interconnect with air-gap has been developed to reduce RC delay time for quick turn-around-time foundry manufacturing. The air-gap method has been successfully applied to 0.25 νm foundry technology. Measurements on ring oscillators confirm that the smallest delay time is indeed achieved with the air-gap method, compared with that using either conventional high-density-plasma (HDP) oxide or low-dielectric-constant spin-on-glass (SOG). In addition, we have also developed fitting equations for the delay time, thus provide a handy method for predicting the RC delay time. The oscillator delay time is also found to be critically dependent on not only the size, but also the position of the air-gap. Best delay time reduction is obtained when the air-gap is positioned in extended both above and below the metal lines to effectively reduce the fringing capacitance.

Buffer for High Performance in CNT Based VLSI Interconnects

2018 ◽  
Vol 24 (8) ◽  
pp. 5975-5981
Author(s):  
A Karthikeyan ◽  
P. S Mallick
Keyword(s):  
Integrated Circuits ◽  
Packing Density ◽  
Power Dissipation ◽  
High Performance ◽  
Critical Path ◽  
Vlsi Interconnects ◽  
Performance Constraints ◽  
Interconnect Delay ◽  
Interconnect Optimization ◽  
Technology Nodes

Integrated circuits (IC’s) are sized for higher performance and packing density. Interconnects are major components to carry signals between transistors. Interconnect delay increases due to increase in length of interconnect. Optimization of interconnects is more essential to improve the performance of integrated circuits. Repeater insertion is an important technique used in optimizing the performance of interconnects in integrated circuits. Repeaters have to be designed to satisfy the performance constraints. In this paper we have designed a new repeater using transistors and analyzed the performance at various bias levels. The Repeater design was implemented at various technology nodes using PTM models and Bulk CMOS. Delay and power dissipation are analyzed for various voltage levels and load levels using Spice simulations. The results show that the proposed repeater has lesser delay compared to the conventional repeater with an increase of power dissipation and they are more suitable for Critical path in VLSI interconnects. They can be applicable for CNT based VLSI interconnects.

Sign in / Sign up

Export Citation Format

Share Document