Novel Global Interconnect structure with improved Elmore Delay Estimation for Low-Power Applications

With advancements in technology, size and speed have been the important facet in VLSI interconnects. Interconnects are known as the basic building block that provide a connection between two or more blocks and have scaling problems that an IC designer faces while designing. As scaling increases, the impact of interconnect in the VLSI circuits became even more important. It controls all the important electrical characteristics on the chip. With scale-down technology, interconnects not only become closer with each other but their dimensions also change which can directly impact the circuit parameters. Certain RC structures have already been defined to control these parameters but in this paper, authors have proposed a new interconnect structure with improved Elmore delay estimation to reduce delay and power consumption in lumped and distributed interconnect circuits using Pulse and Ramp inputs. Further, the proposed model is estimated and verified theoretically. The linear relationship of power consumption and delay for the RC structure has been observed. The proposed structure with improved Elmore delay estimation shows improvement in delay by 64.25% in lumped circuits and 68.75% in distributed circuits in comparison to existing Elmore delay calculations which help in increasing the overall speed of the interconnect circuit.

Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

With the quick progress in the area of digital electronics results in miniaturization of semiconductor Industries. In Deep Sub Micron regime, because of leakage current, power consumption is turn out to be a major issue; hence constant efforts are being made by the researchers for investigating the various ways to minimize this. There are various methods available for the same and out of several available methods use of Carbon Nano-tube technology is a promising way to design low power circuits efficiently. Here new techniques are introduced for the reduction of leakage power. Here in this work, comparison of the main performance parameters of Copper on chip nano-interconnect with CNTFET has been done. We have measured the impact of ION and IOFF current by applying Process variation in CU and CNT- Interconnects with the variation of Tubes at 32nm technology and analysed the performance of the digital circuits with scaling of technology. The different kind of simulation outcomes indicates that by applying 10% of deviation from normal value in different device characteristics parameters such as Length of Gate (LTube) of the Tube, Width (WTube) of the Tube, Threshold Voltage (Vth) of the Tube, Thickness (tot) of Tube and Source & Drain Doping concentration with Cu and CNTFET interconnects for NFET and PFET with the variation of tubes from 1 to 16. All the experimental outcomes are achieved by using HSPICE simulator using SPICE model of CU and CNT at27oC temperature by using 32nm Berkley Predictive Technology module.