MODELLING OF NEXT ZEN MEMORY CELL USING LOW POWER CONSUMING HIGH SPEED NANO DEVICES

2015 ◽  
Vol 04 (04) ◽  
pp. 670-675
Author(s):  
Jayanta Gope .
Keyword(s):  
Low Power ◽  
High Speed ◽  
Memory Cell

High Speed, Low Power Programming in 0.17µm Channel Length NOR-type Floating Gate Flash Memory Cell Free of Drain Turn-On Effects

2004 ◽  
Vol 43 (No. 2A) ◽  
pp. L224-L226
Author(s):  
Chang-Ki Baek ◽  
Yunheub Song ◽  
Bomsoo Kim ◽  
Wu-yun Quan ◽  
Young June Park ◽  
...  
Keyword(s):  
Low Power ◽  
Flash Memory ◽  
High Speed ◽  
Memory Cell ◽  
Channel Length ◽  
Floating Gate ◽  
Turn On ◽  
Flash Memory Cell

scholarly journals Design and Performance Analysis of Low Power High Speed CNTFET Binary Content Addressable Memory Cell for Next Generation Communication Networks

2019 ◽  
Vol 9 (2) ◽  
pp. 8-15
Keyword(s):  
Low Power ◽  
Communication Networks ◽  
High Speed ◽  
Average Power ◽  
Memory Cell ◽  
Dielectric Materials ◽  
Content Addressable Memory ◽  
Adiabatic Logic ◽  
Effect Transistor ◽  
And Performance

In this paper, Carbon Nanotube Field Effect Transistor (CNTFET) based Binary Content Addressable Memory (BCAM) cells are proposed. The adiabatic logic is integrated with the proposed BCAM cells to improve performance. The performance of proposed BCAM cells is presented for various CNTFET parameters such as number of tubes, chirality vector, pitch value, dielectric constant and dielectric materials. It also explores the optimum set of CNTFET parameters for low power and high speed characteristics of the proposed BCAM cells. Simulation results show an improvement in the average power and delay of proposed BCAM cells. The average power of the proposed BCAM cells is in the order of nano watts while the CMOS based BCAM cells is in the order of micro watts. The delay of the proposed BCAM cells is improved by 56.4 %. All simulations are conducted for both CMOS and CNTFET based BCAM cells in HSPICE at 32 nm technology

HIGH SPEED AND LOW POWER 4*4 ARRAY MULTIPLIER DESIGN

2019 ◽  
Vol 7 (1) ◽  
pp. 24
Author(s):  
N. SURESH ◽  
K. S. SHAJI ◽  
KISHORE REDDY M. CHAITANYA ◽  
◽  
◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Array Multiplier

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

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