Less Reliable Page Error Reduction for 3D-TLC NAND Flash Memories with Data Overhead Reduction by 40% and Data-retention Time Increase by 5.0x

Author(s):  
Kyosuke Maeda ◽  
Kyoji Mizoguchi ◽  
Ken Takeuchi
2021 ◽  
pp. 1-1
Author(s):  
Yu-Heng Liu ◽  
Yu-Siang Yang ◽  
Chih-Yuan Tseng ◽  
Wei Lin ◽  
An-Chang Liu ◽  
...  

2020 ◽  
Author(s):  
Zaci Cohen

<p>This article represents a new method for Data Retention failure (DR) in NAND Flash memories by analyzing the <b>charge leakage</b> phenomena. Retention failure accrue when stored data changes its level. This usually happens at and because of a high temperature environment that accelerate leakage.</p> <p>The amount of electron charge in the cell is rather hard to calculate. However, we know that a verification process done at the end of the programming with respect to the amount of charge, is apparently enough to indicate the proper logical level. Moreover, when the cell is exposed to high temperature the charge leaks out but the manufacturer`s guarantee that the memory storage will withstand the JEDS218 standard, this mean that this amount of charge should be enough for 10 years at temperature ambient range of 25÷55°C. Hence, after 10 years, in the worst-case scenario, the amount of charge might be so low that its results can adversely affect its logical level.</p> <p>In our previous work, we found that the programed cell array affected by temperature as shown in figure 1, begin with the average voltage is equal to V<sub>t1</sub> and later, when the leakage occurs, the average voltage decreases while the variation increases.</p>


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