scholarly journals Performance Analysis of an OFDM PHY Scheme with Zero Forcing Equalizer Using Software Defined Radio Platform and USRP

Author(s):  
Ahmad Zainudin ◽  
Amang Sudarsono ◽  
I Gede Puja Astawa

We present an implementation of Zero Forcing (ZF) equalizer in OFDM scheme using Software Defined Radio platform whereas NI USRP-2920 as the Radio Frequency (RF) front-end. ZF equalizer is employed to achieve reliable system at the receiver. Center frequency used for data transmission is 915 MHz. The reliability transmission and the performance of ZF equalizer are measured in term of different symbol mapping (i.e., M-PSK and M-QAM). The IQ rate determines the bandwidth available, whereas good performance is achieved with IQ rate less than 1 MHz.ZF equalizer achieves good performance when using BPSK, QPSK and 16-QAM modulation techniques. By applying ZF equalizer, bit error on BPSK and QPSK modulations can be reduced from 29,16% and 39,06% into 0%. This advantage of ZF equalizer also is able to press the bit error on 16- QAM and 64-QAM modulations into 3,125% and 8,85%, respectively.Keywords: OFDM,SDR, USRP,Zero Forcing Equalizer

2014 ◽  
Vol 926-930 ◽  
pp. 2503-2507
Author(s):  
Wen Kai Liu ◽  
Peng Wang ◽  
Jian Cui

RF front-end is an important part of the communication system. It realizes the functions such as low noise amplifier application, filtering and mixing, completes the conversion between the IF signal and the RF signal, and ensures effective communication system flexibility and versatility. In the paper, according to the superheterodyne structure, a receiver RF front-end has been designed. The total gain of the link circuit is more than 100 dB, with 50 dB AGC range, the center frequency is 750 MHz with 100MHz bandwidth, local oscillator (LO) signal with frequency 935MHz is generated by PLL and the stability is-82dBc/Hz@1KHz.


Author(s):  
MANJULA. K ◽  
PRATHIBHA. S. K

In this paper, A Software-Defined Radio (SDR) RF front-end is presented that contains merged LNA and mixers, VGAs, and frequency synthesizer, supporting various wireless communication standards in 0.1-2 GHz while guaranteeing a power/performance trade-off at any time. The proposed low power RF front-end uses the folded and current reuse techniques. for 0.18 um RF CMOS technology with 1.8V supply voltage. In the receive path the proposed design achieves a Noise Figure of 3.8 dB at 160 MHz and 5.5 dB at 2GHz. The Output-referred 3rd-order Intercept Point (OIP3) is high up to 21.3 dBm at 800 MHz. The voltage gain of the front- end is between 16-44 dB. The phase mismatch of LO quadrature signals is lower than 3deg.It consumes 13.8 mW at the 1.7V supply.


Author(s):  
S.M. Shajedul Hasan ◽  
Randall Nealy ◽  
Terrence J. Brisebois ◽  
Timothy R. Newman ◽  
Tamal Bose ◽  
...  

2019 ◽  
Vol 26 (1) ◽  
pp. 98-105 ◽  
Author(s):  
Oskar Mężyk ◽  
Michał Doligalski ◽  
Ryszard Rybski

Abstract In the work a method of latency measurement in software defined radio (SDR) is proposed and validated. The test setup uses customer grade GNSS modules as reference time sources and enables relative delay calculation between signals received directly and those bypassed through SDR platform. The method is hardware agnostic in a sense, that it does not involve any custom software or hardware modifications. Tests that compare reported carrier-to-noise ratio and positioning errors were performed to prove functionality of such system. Additionally, authors measured several gnuradio blocks with respect to their impact on total latency introduced into signal path. All tests were performed on a bladeRF low-cost RF front-end. Minimum observed latency for the signal was below 10 ms.


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