scholarly journals Analysis of multibackground memory testing techniques

2010 ◽  
Vol 20 (1) ◽  
pp. 191-205 ◽  
Author(s):  
Ireneusz Mrozek
Keyword(s):  
Initial Conditions ◽  
Fault Coverage ◽  
Fault Model ◽  
Memory Testing ◽  
March Test ◽  
Transition Faults ◽  
Complex Fault ◽  
Pattern Sensitive Faults ◽  
Testing Techniques ◽  
March Tests

Analysis of multibackground memory testing techniquesMarch tests are widely used in the process of RAM testing. This family of tests is very efficient in the case of simple faults such as stuck-at or transition faults. In the case of a complex fault model—such as pattern sensitive faults—their efficiency is not sufficient. Therefore we have to use other techniques to increase fault coverage for complex faults. Multibackground memory testing is one of such techniques. In this case a selected March test is run many times. Each time it is run with new initial conditions. One of the conditions which we can change is the initial memory background. In this paper we compare the efficiency of multibackground tests based on four different algorithms of background generation.

scholarly journals Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests

2008 ◽  
Vol 18 (3) ◽  
pp. 329-339 ◽  
Author(s):  
Svetlana Yarmolik
Keyword(s):  
Selection Process ◽  
Fault Coverage ◽  
Memory Test ◽  
Memory Testing ◽  
Test Technique ◽  
Test Execution ◽  
Sequence Selection ◽  
Pattern Sensitive Faults ◽  
March Tests ◽  
Very High

Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March TestsIt is widely known that pattern sensitive faults are the most difficult faults to detect during the RAM testing process. One of the techniques which can be used for effective detection of this kind of faults is the multi-background test technique. According to this technique, multiple-run memory test execution is done. In this case, to achieve a high fault coverage, the structure of the consecutive memory backgrounds and the address sequence are very important. This paper defines requirements which have to be taken into account in the background and address sequence selection process. A set of backgrounds which satisfied those requirements guarantee us to achieve a very high fault coverage for multi-background memory testing.

scholarly journals Construction and application of march tests for pattern sensitive memory faults detection

Informatics ◽  
2021 ◽  
Vol 18 (1) ◽  
pp. 25-42
Author(s):  
V. N. Yarmolik ◽  
V. A. Levantsevich ◽  
D. V. Demenkovets ◽  
I. Mrozek
Keyword(s):  
Fault Detection ◽  
Multiple Testing ◽  
High Efficiency ◽  
Fault Coverage ◽  
Memory Cells ◽  
March Test ◽  
Storage Devices ◽  
Coupon Collector ◽  
March Tests ◽  
Analytical Expressions

The urgency of the problem of testing storage devices of modern computer systems is shown. The mathematical models of their faults and the methods used for testing the most complex cases by classical march tests are investigated. Passive pattern sensitive faults (PNPSFk) are allocated, in which arbitrary k from N memory cells participate, where k << N, and N is the memory capacity in bits. For these faults, analytical expressions are given for the minimum and maximum fault coverage that is achievable within the march tests. The concept of a primitive is defined, which describes in terms of march test elements the conditions for activation and fault detection of PNPSFk of storage devices. Examples of march tests with maximum fault coverage, as well as march tests with a minimum time complexity equal to 18N are given. The efficiency of a single application of tests such as MATS ++, March C− and March PS is investigated for different number of k ≤ 9 memory cells involved in PNPSFk fault. The applicability of multiple testing with variable address sequences is substantiated, when the use of random sequences of addresses is proposed. Analytical expressions are given for the fault coverage of complex PNPSFk faults depending on the multiplicity of the test. In addition, the estimates of the mean value of the multiplicity of the MATS++, March C− and March PS tests, obtained on the basis of a mathematical model describing the problem of the coupon collector, and ensuring the detection of all k2k PNPSFk faults are given. The validity of analytical estimates is experimentally shown and the high efficiency of PNPSFk fault detection is confirmed by tests of the March PS type.

Two-Run RAM March Testing with Address Decimation

2016 ◽  
Vol 26 (02) ◽  
pp. 1750031 ◽  
Author(s):  
Ireneusz Mrozek ◽  
Vyacheslav Yarmolik
Keyword(s):  
Selection Process ◽  
Random Access ◽  
Test Session ◽  
Analytical Investigation ◽  
Fault Coverage ◽  
Test Procedures ◽  
March Test ◽  
Sequence Selection ◽  
Time Standard ◽  
March Tests

Conventional march memory tests have high fault coverage, especially for simple faults like stack-at fault (SAF), transition fault (TF) or coupling fault (CF). The same-time standard march tests, which are based on only one run, are becoming insufficient for complex faults like pattern-sensitive faults (PSFs). To increase fault coverage, the multi-run transparent march test algorithms have been used. This solution is especially suitable for built-in self-test (BIST) implementation. The transparent BIST approach presents the incomparable advantage of preserving the content of the random access memory (RAM) after testing. We do not need to save the memory content before the test session or to restore it at the end of the session. Therefore, these techniques are widely used in critical applications (medical electronics, railway control, avionics, telecommunications, etc.) for periodic testing in the field. Unfortunately, in many cases, there is very limited time for such test sessions. Taking into account the above limitations, we focus on short, two-run march test procedures based on counter address sequences. The advantage of this paper is that it defines requirements that must be taken into account in the address sequence selection process and presents a deeply analytical investigation of the optimal address decimation parameter. From the experiments we can conclude that the fault coverage of the test sessions generated according to the described method is higher than in the case of pseudorandom address sequences. Moreover, the benefit of this solution seems to be low hardware overhead in implementation of an address generator.

scholarly journals Automated Search-Based Robustness Testing for Autonomous Vehicle Software

2016 ◽  
Vol 2016 ◽  
pp. 1-15 ◽  
Author(s):  
Kevin M. Betts ◽  
Mikel D. Petty
Keyword(s):  
Monte Carlo ◽  
Performance Metrics ◽  
Initial Conditions ◽  
Autonomous Vehicle ◽  
Vehicle Control ◽  
Test Case ◽  
Test Cases ◽  
Control Software ◽  
Robustness Testing ◽  
Testing Techniques

Autonomous systems must successfully operate in complex time-varying spatial environments even when dealing with system faults that may occur during a mission. Consequently, evaluating the robustness, or ability to operate correctly under unexpected conditions, of autonomous vehicle control software is an increasingly important issue in software testing. New methods to automatically generate test cases for robustness testing of autonomous vehicle control software in closed-loop simulation are needed. Search-based testing techniques were used to automatically generate test cases, consisting of initial conditions and fault sequences, intended to challenge the control software more than test cases generated using current methods. Two different search-based testing methods, genetic algorithms and surrogate-based optimization, were used to generate test cases for a simulated unmanned aerial vehicle attempting to fly through an entryway. The effectiveness of the search-based methods in generating challenging test cases was compared to both a truth reference (full combinatorial testing) and the method most commonly used today (Monte Carlo testing). The search-based testing techniques demonstrated better performance than Monte Carlo testing for both of the test case generation performance metrics: (1) finding the single most challenging test case and (2) finding the set of fifty test cases with the highest mean degree of challenge.

scholarly journals Research on Automatic Construction Method of Three-Dimensional Complex Fault Model

Minerals ◽  
2021 ◽  
Vol 11 (8) ◽  
pp. 893
Author(s):  
Chi Zhang ◽  
Xiaolin Hou ◽  
Mao Pan ◽  
Zhaoliang Li
Keyword(s):  
Three Dimensional ◽  
Geological Structure ◽  
Fault Model ◽  
Construction Method ◽  
Model Construction ◽  
Automatic Construction ◽  
Complex Fault ◽  
Resource Exploration ◽  
Fault Structures ◽  
Manual Interaction

Three-dimensional complex fault modeling is an important research topic in three-dimensional geological structure modeling. The automatic construction of complex fault models has research significance and application value for basic geological theories, as well as engineering fields such as geological engineering, resource exploration, and digital mines. Complex fault structures, especially complex fault networks with multilevel branches, still require a large amount of manual participation in the characterization of fault transfer relationships. This paper proposes an automatic construction method for a three-dimensional complex fault model, including the generation and optimization of fault surfaces, automatic determination of the contact relationship between fault surfaces, and recording of the model. This method realizes the automatic construction of a three-dimensional complex fault model, reduces the manual interaction in model construction, improves the automation of fault model construction, and saves manual modeling time.

scholarly journals Fault Modeling of ECL for High Fault Coverage of Physical Defects

VLSI Design ◽  
1996 ◽  
Vol 4 (3) ◽  
pp. 231-242 ◽  
Author(s):  
Sankaran M. Menon ◽  
Yashwant K. Malaiya ◽  
Anura P. Jayasumana
Keyword(s):  
Logic Gates ◽  
Design For Testability ◽  
Fault Modeling ◽  
Fault Coverage ◽  
Fault Model ◽  
Line Detection ◽  
Lower Power ◽  
On Line ◽  
Physical Defects

Bipolar Emitter Coupled Logic (ECL) devices can now be fabricated at higher densities and consumes much lower power. Behaviour of simple and complex ECL gates are examined in the presence of physical faults. The effectiveness of the classical stuck-at model in representing physical failures in ECL gates is examined. It is shown that the conventional stuck-at fault model cannot represent a majority of circuit level faults. A new augmented stuck-at fault model is presented which provides a significantly higher coverage of physical failures. The model may be applicable to other logic families that use logic gates with both true and complementary outputs. A design for testability approach is suggested for on-line detection of certain error conditions occurring in gates with true and complementary outputs which is a normal implementation for ECL devices.

Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model

2006 ◽  
Vol 25 (12) ◽  
pp. 2954-2964 ◽  
Author(s):  
Mahilchi Milir Vaseekar Kumar ◽  
Spyros Tragoudas ◽  
Sreejit Chakravarty ◽  
Rathish Jayabharathi
Keyword(s):  
Fault Coverage ◽  
Fault Model ◽  
Delay Fault ◽  
Sequential Logic
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